From: Ju-Zhe Zhong
Sorry for resend this patch, I found I miss commit a file.
1. vector.md: remove tail && mask policy operand for mask mode operations since
we don't need them according to RVV ISA.
2. riscv-v.cc: adapt emit_pred_op for mask mode predicated mov since all RVV
modes
includin
Actually, I am strongly support those stuff keep merge to trunk until
February, my goal is intrinsic support for vector, but not including any
vectorization like SLP or Loop vectorization, the most critical part is the
vsetvli which is the mode switching, and its almost done.
Those part is kind of
Yeah, I personally want to support RVV intrinsics in GCC13.
As RVV intrinsic is going to release soon next week.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2022-11-29 09:38
To: Jeff Law
CC: 钟居哲; gcc-patches; palmer
Subject: Re: [PATCH] RISC-V: Add attributes for VSETVL PASS
Actually, I am st
on 2022-11-28 23:39 Jeff Law wrote:
>
>
>On 11/27/22 19:14, Feng Wang wrote:
>> From: wangfeng
>>
>> There is no Immediate operand of ins "rol" accroding to the B-ext,
>> so the immediate operand should be loaded into register at first.
>> But we can convert it to the ins "rori" or "roriw", and t
On Mon, Nov 28, 2022 at 6:40 AM Martin Liška wrote:
>
> On 11/11/22 02:26, liuhongt via Gcc-patches wrote:
> >2 years ago, ARM folks support HWASAN[1] in GCC[2], and introduced
> > several
> > target hooks(Many thanks to their work) so other backends can do similar
> > things if they have sim
On Mon, Nov 28, 2022 at 10:40 PM Martin Liška wrote:
>
> On 11/11/22 02:26, liuhongt via Gcc-patches wrote:
> >2 years ago, ARM folks support HWASAN[1] in GCC[2], and introduced
> > several
> > target hooks(Many thanks to their work) so other backends can do similar
> > things if they have si
On Mon, 28 Nov 2022 17:46:16 PST (-0800), juzhe.zh...@rivai.ai wrote:
Yeah, I personally want to support RVV intrinsics in GCC13.
As RVV intrinsic is going to release soon next week.
OK, that's fine with me -- I was leaning that way, and I think Jeff only
had a weak opposition. Are there any
In case of RVV intrinsic support, there is no changes outside RISC-V backend
since we don't do the autovectorization support for now.
I will postpone autovectorization until GCC14 is open.
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2022-11-29 10:56
To: juzhe.zhong
CC: Kito Cheng; jeffreya
On Mon, 28 Nov 2022 19:07:24 PST (-0800), juzhe.zh...@rivai.ai wrote:
In case of RVV intrinsic support, there is no changes outside RISC-V backend
since we don't do the autovectorization support for now.
OK, I'm fine with that. Sounds like Kito is too?
I will postpone autovectorization until
Hi Jeff,
Thanks a lot for your comments!
Jeff Law writes:
> On 11/22/22 19:58, Jiufu Guo wrote:
>> Hi Jeff,
>>
>> Thanks a lot for your comments!
>>
>> Jeff Law writes:
>>
>>> On 11/20/22 20:07, Jiufu Guo wrote:
Jiufu Guo writes:
> Hi,
>
> As mentioned in the previous
On 11/28/22 19:56, Palmer Dabbelt wrote:
On Mon, 28 Nov 2022 17:46:16 PST (-0800), juzhe.zh...@rivai.ai wrote:
Yeah, I personally want to support RVV intrinsics in GCC13. As RVV
intrinsic is going to release soon next week.
OK, that's fine with me -- I was leaning that way, and I think Jeff
On 11/28/22 18:53, Feng Wang wrote:
on 2022-11-28 23:39 Jeff Law wrote:
On 11/27/22 19:14, Feng Wang wrote:
From: wangfeng
There is no Immediate operand of ins "rol" accroding to the B-ext,
so the immediate operand should be loaded into register at first.
But we can convert it to the in
On Mon, 28 Nov 2022 20:49:00 PST (-0800), jeffreya...@gmail.com wrote:
On 11/28/22 19:56, Palmer Dabbelt wrote:
On Mon, 28 Nov 2022 17:46:16 PST (-0800), juzhe.zh...@rivai.ai wrote:
Yeah, I personally want to support RVV intrinsics in GCC13. As RVV
intrinsic is going to release soon next week
On Mon, Nov 28, 2022 at 9:06 PM liuhongt wrote:
>
> For __builtin_ia32_vec_set_v16qi (a, -1, 2) with
> !flag_signed_char. it's transformed to
> __builtin_ia32_vec_set_v16qi (_4, 255, 2) in the gimple,
> and expanded to (const_int 255) in the rtl. But for immediate_operand,
> it expects (const_int
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