Re: [PATCH v2 00/10] [RISC-V] Atomics improvements [PR100265/PR100266]

On Wed, Oct 12, 2022 at 07:16:20PM +0200, Andrea Parri wrote: > > > > +Andrea, in case he has time to look at the memory model / ABI > > > > issues. > > > +Jeff, who was offering to help when the threads got crossed. I'd punted on > > a lot of this in the hope Andrea could help out, as I'

Re: [PATCH v4] testsuite: Sanitize fails for SP FPU on Arm

On 2022-10-20 20:19, Joseph Myers wrote: On Wed, 19 Oct 2022, Torbjörn SVENSSON via Gcc-patches wrote: This patch stops reporting fails for Arm targets with single precision floating point unit for types wider than 32 bits (the width of float on arm-none-eabi). As reported in PR102017, fenv

Re: [COMMITTED] Replace finite_operands_p with maybe_isnan.

On Thu, Oct 20, 2022 at 8:59 PM Mikael Morin wrote: > > Le 20/10/2022 à 20:56, Mikael Morin a écrit : > > > > Doesn't this miss a check of flag_finite_math_only to be strictly > > equivalent? You keep that check for the two-arguments case, so I guess > > it's not redundant? > > Well, the check is

Re: Add 'gcc.dg/tree-ssa/pr107195-3.c' [PR107195] (was: Add 'c-c++-common/torture/pr107195-1.c' [PR107195] (was: [COMMITTED] [PR107195] Set range to zero when nonzero mask is 0.))

Hi! On 2022-10-20T14:23:33+0200, Aldy Hernandez wrote: >> I understand 'r & 3' to be logically equivalent to '(r & 2) && (r & 1)', >> right? > > For r == 2, r & 3 == 2, whereas (r & 2) && (r & 1) == 0, so no? Thanks, and now please let me crawl back under my stone, embarassing... That'd rather b

[COMMITTED] Add op[12]_range for UNORDERED_LT entries in range-op.

In auditing the UNORDERED range-op code I noticed the UNLT_EXPR entry was missing op1_range and op2_range operators. That is, we were missing the ability to unwind back through an UNLT_EXPR. gcc/ChangeLog: * range-op-float.cc (foperator_unordered_lt::op1_range): New. (foperator_u

[COMMITTED] [PR c++/106654] Handle non-irange ranges in get_range_global for default defs.

With the upcoming [[assume]] work, Andrew has pointed out that non-irange ranges are not handled in get_range_global for SSA_NAME_IS_DEFAULT_DEF. This patch fixes the oversight. PR c++/106654 gcc/ChangeLog: * value-query.cc (get_range_global): Handle non integer ranges for

[PATCH RFA] tree: add build_string_literal overloads

Tested x86_64-pc-linux-gnu, OK for trunk? -- >8 -- Simplify several calls to build_string_literal by not requiring redundant strlen or IDENTIFIER_* in the caller. I also corrected a wrong comment on IDENTIFIER_LENGTH. gcc/ChangeLog: * tree.h (build_string_literal): New one-argument ove

[PATCH] cpp/remap: Only override if string matched

For systems with HAVE_DOS_BASED_FILE_SYSTEM set, only override the pointer if the backslash pattern matches. Output without this patch: .../gcc/testsuite/gcc.dg/cpp/pr71681-2.c:5:10: fatal error: a/t2.h: No such file or directory With patch applied, no output and the test case succeeds. libcpp/

Re: Remove support for Intel MIC offloading

Hi Jakub, Tobias! On 2022-10-20T13:15:43+0200, I wrote: > I'm proposing the attached "Remove support for Intel MIC offloading" Can you please confirm: > --- a/gcc/config/i386/i386-options.cc > +++ b/gcc/config/i386/i386-options.cc > @@ -307,10 +307,6 @@ ix86_omp_device_kind_arch_isa (enum > omp

[committed] wwwdocs: *: Use instead of

With commit bf9d87193528c81b076ff463ff5591e960b6ed63 we replaced by . It now turns out we have gathered some s, sans the space before the slash, over the years. Convert those to plain as well. Pushed. --- htdocs/branch-closing.html | 4 +-- htdocs/contribute.html | 2 +- htdocs/

Re: Add 'gcc.dg/tree-ssa/pr107195-3.c' [PR107195] (was: Add 'c-c++-common/torture/pr107195-1.c' [PR107195] (was: [COMMITTED] [PR107195] Set range to zero when nonzero mask is 0.))

On Thu, Oct 20, 2022 at 9:22 PM Thomas Schwinge wrote: > > Hi! > > On 2022-10-20T14:23:33+0200, Aldy Hernandez wrote: > >> I understand 'r & 3' to be logically equivalent to '(r & 2) && (r & 1)', > >> right? > > > > For r == 2, r & 3 == 2, whereas (r & 2) && (r & 1) == 0, so no? > > Thanks, and n

Re: [PATCH 0/6] Add Intel Sierra Forest Instructions

> Thanks for giving me a chance to test, this seems OK on Darwin (no large-scale > fallout, anyway) .. > Good to hear that. > I tested the ise046 branch which looks like it collects several of the posted > patch > series, so I’ve covered those too. (not had a chance to test on AVX512 yet, > but i

Re: [PATCH] Support Intel AVX-IFMA

On Wed, Oct 19, 2022 at 2:04 PM Hongyu Wang via Gcc-patches wrote: > > Hi, > > Here is the update patch that align the implementation to AVX-VNNI, > and corrects some spelling error for AVX512IFMA pattern. > > Bootstrapped/regtested on x86_64-pc-linux-gnu and sde. Ok for trunk? Ok for this one. >

Re: [PATCH v2] Support Intel AVX-VNNI-INT8

On Wed, Oct 19, 2022 at 9:41 AM Hongtao Liu wrote: > > On Tue, Oct 18, 2022 at 5:13 PM Haochen Jiang via Gcc-patches > wrote: > > > > From: Kong Lingling > > > > Hi all, > > > > This is our v2 patch on AVX-VNNI-INT8. This main change in this patch is to > > rename the previous UNSPEC_VPMADDxxx t

Re: [PATCH] i386: Auto vectorize sdot_prod, udot_prod with VNNIINT8 instruction.

On Wed, Oct 19, 2022 at 9:43 AM Hongtao Liu wrote: > > On Tue, Oct 18, 2022 at 5:18 PM Haochen Jiang via Gcc-patches > wrote: > > > > Hi all, > > > > We would like to add one more patch to enhance the codegen with avxvnniint8. > > Also renamed two awkward named mode_attr to make them more aligned

Ping^3 [PATCH V2] Add attribute hot judgement for INLINE_HINT_known_hot hint.

Hi Honza, Gentle ping https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601934.html gcc/ChangeLog * ipa-inline-analysis.cc (do_estimate_edge_time): Add function attribute judgement for INLINE_HINT_known_hot hint. gcc/testsuite/ChangeLog: * gcc.dg/ipa/inlinehint-6.c: New test. --

RE: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM

> -Original Message- > From: Segher Boessenkool > Sent: Friday, October 21, 2022 2:54 AM > To: Jiang, Haochen > Cc: gcc-patches@gcc.gnu.org; rguent...@suse.de; Liu, Hongtao > ; ubiz...@gmail.com; richard.earns...@arm.com; > richard.sandif...@arm.com; marcus.shawcr...@arm.com; > kyrylo.

Re: [PATCH] RISC-V: Add RVV intrinsic basic framework.

Verified, committed to trunk. On Mon, Oct 17, 2022 at 4:21 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add gt files since function_instance is GTY ((user)). > * config/riscv/riscv-builtins.cc (riscv_init_builtins): Add RVV > intrinsic framework. >

Re: [PATCH] RISC-V: Add RVV vsetvl/vsetvlmax intrinsics and tests.

Verified, committed to trunk. On Mon, Oct 17, 2022 at 4:37 PM wrote: > > From: Ju-Zhe Zhong > > gcc/ChangeLog: > > * config.gcc: Add riscv-vector-builtins-bases.o and > riscv-vector-builtins-shapes.o > * config/riscv/riscv-vector-builtins.cc (DEF_RVV_I_OPS): New macro. >

[PATCH] RISC-V: Add type attribute for atomic instructions.

gcc/ChangeLog: * config/riscv/riscv.md: Add atomic type attribute. * config/riscv/sync.md: Add atomic type for atomic instructions. --- gcc/config/riscv/riscv.md | 2 +- gcc/config/riscv/sync.md | 15 ++- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git

Re: [PATCH] xtensa: Make register A0 allocable for the CALL0 ABI

Hi Suwa-san, On Thu, Oct 20, 2022 at 7:58 PM Takayuki 'January June' Suwa wrote: > > This patch offers an additional allocable register by RA for the CALL0 > ABI. > > > Register a0 holds the return address upon entry to a function, but > > unlike the windowed register ABI, it is not reserved for

[committed] Don't build readline/libreadline.a, when --with-system-readline is supplied

Hi, [ Committed as obvious as per https://gcc.gnu.org/legacy-ml/gcc-patches/2018-12/msg00299.html . ] https://sourceware.org/bugzilla/show_bug.cgi?id=18632 The bundled libreadline is always built, even if the system is ./configure'd --with-system-readline and the build libreadline.a is not used.

<    1   2