Hi Suwa-san,
On Fri, Jun 10, 2022 at 8:28 AM Takayuki 'January June' Suwa
wrote:
>
> This patch revises the previous implementation of constant synthesis.
>
> First, changed to use define_split machine description pattern and to run
> after reload pass, in order not to interfere some optimization
On 2022/06/11 16:58, Max Filippov wrote:
Hi Suwa-san,
hi!
this change results in a bunch of ICEs in the tests like this:
during RTL pass: split2
gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c: In function 'f':
gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c:13:1: internal
compiler e
On Sat, Jun 11, 2022 at 1:31 AM Takayuki 'January June' Suwa
wrote:
> > this change results in a bunch of ICEs in the tests like this:
> > during RTL pass: split2
> > gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c: In function 'f':
> > gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c:13:
On Sat, Jun 11, 2022 at 1:31 AM Takayuki 'January June' Suwa
wrote:
> > this change results in a bunch of ICEs in the tests like this:
> > during RTL pass: split2
> > gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c: In function 'f':
> > gcc/gcc/testsuite/gcc.c-torture/compile/20120727-1.c:13:
(resent with correct address for Iain)
This is the same sort of problem as in PR80204: at present, GCC 11 & 12 assume
that if the
OS version is >= 20, the compiler should see --mmacosx-version-min={major -
9}.{minor -1}.0,
e.g. for OS version 21.3.0 that would be 12.2.0 (the linker sees
-maco
thanks for your report.
On 2022/06/11 18:05, Max Filippov wrote:
It prints
(symbol_ref/f:SI ("*.LC1") [flags 0x2] )
ah, i understand it... that is Pmode (synonym of SImode) of a memory
address that points to 'u.f'.
thus, the correct handling is to fail the split pattern.
---
gcc/config/xte
Hi Simon,
thanks for the patch.
> On 11 Jun 2022, at 10:17, Simon Wright wrote:
>
> (resent with correct address for Iain)
>
> This is the same sort of problem as in PR80204: at present, GCC 11 & 12
> assume that if the
> OS version is >= 20, the compiler should see --mmacosx-version-min={ma
> Well, so should we add TSAN_SUPPORTED=yes for MIPS64 in
> libsanitizer/configure.tgt first? I'll try this on my MIPS64 in a few
> days.
Just tried TSAN_SUPPORTED=yes with asynchronous unwind tables enabled,
but I got some strange test failures for tls_race.c:
FAIL: c-c++-common/tsan/tls_race
On Fri, Jun 10, 2022 at 7:22 AM Xi Ruoyao wrote:
>
> On Thu, 2022-06-09 at 16:04 -0400, Eric Gallager via Gcc-patches wrote:
> > Hi, I'd like to ping this patch:
> > https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596126.html
> > (cc-ing the build machinery maintainers listed in MAINTAINERS th
Here is a brief synopsis of the new linking implementation.
Completed: runtime module dependency resolution, IR scaffold and IR
runtime dependency graph and the compiler driver.
Todo: per module ctors.
The proposed road map: once helloworld links using the new scheme I
plan to git push the upd
On 11 Jun 2022, at 11:37, Iain Sandoe wrote:
>
> Hi Simon,
>
> thanks for the patch.
>
>> On 11 Jun 2022, at 10:17, Simon Wright wrote:
>>
>> (resent with correct address for Iain)
>>
>> This is the same sort of problem as in PR80204: at present, GCC 11 & 12
>> assume that if the
>> OS ver
On Fri, Jun 10, 2022 at 8:28 PM H.J. Lu wrote:
>
> Since F16C and VAES are only usable with AVX, require AVX for F16C and
> VAES.
>
> OK for master and release branches?
>
> Thanks.
>
> H.J.
> ---
> libgcc/105920
> * common/config/i386/cpuinfo.h (get_available_features): Require
>
Hi Simon,
> On 11 Jun 2022, at 20:23, Simon Wright wrote:
>
> On 11 Jun 2022, at 11:37, Iain Sandoe wrote:
>>
>> Hi Simon,
>>
>> thanks for the patch.
>>
>>> On 11 Jun 2022, at 10:17, Simon Wright wrote:
>>>
>>> (resent with correct address for Iain)
>>>
>>> This is the same sort of probl
On Thu, Jun 9, 2022 at 9:26 PM Takayuki 'January June' Suwa
wrote:
>
> umulsidi3 is faster than umuldi3 even if library call, and is also
> prerequisite for fast constant division by multiplication.
>
> gcc/ChangeLog:
>
> * config/xtensa/xtensa.md (mulsidi3, umulsidi3):
> Split int
On Thu, Jun 9, 2022 at 9:26 PM Takayuki 'January June' Suwa
wrote:
>
> This patch implements a new target-specific relative RTL insn cost function
> because of suboptimal cost estimation by default, and fixes several "length"
> insn attributes (related to the cost estimation).
>
> And also introdu
From: Takayuki 'January June' Suwa
Now apply to almost any size of aligned block under such circumstances.
gcc/ChangeLog:
* config/xtensa/xtensa.cc (xtensa_expand_block_set_small_loop):
Pass through the block length / loop count conditions if
zero-overhead looping is con
From: Takayuki 'January June' Suwa
This patch revises the previous implementation of constant synthesis.
First, changed to use define_split machine description pattern and to run
after reload pass, in order not to interfere some optimizations such as
the loop invariant motion.
Second, not only
gcc/testsuite/
* g++.target/xtensa/pr95571.C (__xtensa_libgcc_window_spill):
New definition.
---
gcc/testsuite/g++.target/xtensa/pr95571.C | 6 ++
1 file changed, 6 insertions(+)
diff --git a/gcc/testsuite/g++.target/xtensa/pr95571.C
b/gcc/testsuite/g++.target/xtensa/pr95571.
This patch introduces funnel shifter utilization, and rearranges existing
"per-byte shift" insn patterns.
gcc/ChangeLog:
* config/xtensa/predicates.md (logical_shift_operator,
xtensa_shift_per_byte_operator): New predicates.
* config/xtensa/xtensa-protos.h (xtensa_shlrd_w
No need to describe the "false side" conditional insn patterns anymore.
gcc/ChangeLog:
* config/xtensa/xtensa-protos.h (xtensa_emit_branch):
Remove the first argument.
(xtensa_emit_bit_branch): Remove it because now called only from the
output statement of *bittru
In Xtensa ISA, there is no single machine instruction that calculates unary
bitwise negation, but a few similar fused instructions are exist:
"BALL Ax, Ay, label" // if ((~Ax & Ay) == 0) goto label;
"BNALL Ax, Ay, label" // if ((~Ax & Ay) != 0) goto label;
These instructions have never be
This patch offers several insn-and-split patterns for bitwise AND with
register and constant that cannot fit into a "MOVI Ax, simm12" instruction,
but can be represented as:
i. 1's least significant N bits and the others 0's (17 <= N <= 31)
ii. 1's most significant N bits and the others 0's (1
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