Gentle ping:
https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587311.html
on 2021/12/23 上午10:12, Kewen.Lin via Gcc-patches wrote:
> Hi,
>
> There is one hunk checking for functions with target attribute/pragma
> have the same altivec abi as the one of main_target_opt, it can update
> both
Gentle ping:
https://gcc.gnu.org/pipermail/gcc-patches/2021-December/587449.html
on 2021/12/29 下午5:36, Kewen.Lin via Gcc-patches wrote:
> Hi,
>
> When TARGET_AVOID_XFORM is set, we turn off VSX. But at least from
> ISA3.0 (Power9), we support DQ form vector load/store. This patch
> is to make
On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
>
> Hi,
>
> This patch is to fix register constraint v with
> rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTIVEC_REGS,
> just like some other existing register constraints with
> RS6000_CONSTRAINT_*.
>
> I happened to see this and hope it's
On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
>
> Hi,
>
> This patch is to clean up some codes with GET_MODE_UNIT_SIZE or
> GET_MODE_NUNITS, which can use known constant instead.
I'll let Segher decide, but often the additional code is useful
self-documentation instead of magic constants. Or
Hi David,
on 2022/1/13 上午11:07, David Edelsohn wrote:
> On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
>>
>> Hi,
>>
>> This patch is to fix register constraint v with
>> rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTIVEC_REGS,
>> just like some other existing register constraints with
>
On Wed, Jan 12, 2022 at 10:38 PM Kewen.Lin wrote:
>
> Hi David,
>
> on 2022/1/13 上午11:07, David Edelsohn wrote:
> > On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
> >>
> >> Hi,
> >>
> >> This patch is to fix register constraint v with
> >> rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTI
on 2022/1/13 上午11:44, David Edelsohn wrote:
> On Wed, Jan 12, 2022 at 10:38 PM Kewen.Lin wrote:
>>
>> Hi David,
>>
>> on 2022/1/13 上午11:07, David Edelsohn wrote:
>>> On Wed, Jan 12, 2022 at 8:56 PM Kewen.Lin wrote:
Hi,
This patch is to fix register constraint v with
rs600
From: wwwhhhyyy
Hi,
For GoldenCove micro-architecture, force insert zero-idiom in asm
template to break false dependency of dest register for several insns.
The related insns are:
VPERM/D/Q/PS/PD
VRANGEPD/PS/SD/SS
VGETMANTSS/SD/SH
VGETMANDPS/PD - mem version only
VPMULLQ
VFMULCSH/PH
VFCMULCSH/
On Thu, Jan 13, 2022 at 8:28 AM Hongyu Wang wrote:
>
> From: wwwhhhyyy
>
> Hi,
>
> For GoldenCove micro-architecture, force insert zero-idiom in asm
> template to break false dependency of dest register for several insns.
>
> The related insns are:
>
> VPERM/D/Q/PS/PD
> VRANGEPD/PS/SD/SS
> VGETMA
On Thu, Jan 13, 2022 at 2:53 AM Jiang, Haochen wrote:
>
> Hi Uros,
>
> Has fixed that format issue with this new patch. Ok for trunk?
The patch was already approved in my previous message, so no need to
re-approve it. I'm sure you are able to move one brace to a new
position without another revie
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