Re: [PATCH 6/13] v2 Use new per-location warning APIs in the C++ front end

2021-06-24 Thread Martin Sebor via Gcc-patches
On 6/23/21 11:12 PM, Jeff Law wrote: On 6/4/2021 3:42 PM, Martin Sebor via Gcc-patches wrote: The attached patch replaces the uses of TREE_NO_WARNING in the C++ front end with the new suppress_warning(), warning_suppressed_p(), and copy_warning() APIs. gcc-no-warning-cp.diff Add support for

Re: [PATCH 10/13] v2 Use new per-location warning APIs in the middle end

2021-06-24 Thread Martin Sebor via Gcc-patches
On 6/23/21 11:15 PM, Jeff Law wrote: On 6/4/2021 3:43 PM, Martin Sebor via Gcc-patches wrote: The attached patch introduces declarations of the new suppress_warning(), warning_suppressed_p(), and copy_warning() APIs, and replaces the uses of TREE_NO_WARNING in the middle end with them. gcc-no

Re: [PATCH] x86: Compile CPUID functions with -mgeneral-regs-only

2021-06-24 Thread Hongtao Liu via Gcc-patches
On Fri, Jun 25, 2021 at 12:13 AM Uros Bizjak via Gcc-patches wrote: > > On Thu, Jun 24, 2021 at 2:12 PM H.J. Lu wrote: > > > > CPUID functions are used to detect CPU features. If vector ISAs > > are enabled, compiler is free to use them in these functions. Add > > __attribute__ ((target("genera

Re: [PATCH resend] testsuite: avoid no-stack-protector-attr-3 fail on mips*-*-*

2021-06-24 Thread Xi Ruoyao via Gcc-patches
On Thu, 2021-06-24 at 00:05 -0600, Jeff Law wrote: > > > On 6/22/2021 3:44 AM, Xi Ruoyao via Gcc-patches wrote: > > [Resend because the original subject missed "[PATCH]" and the path > > in > > ChangeLog is wrong.] > > > > On MIPS a call to __stack_chk_fail needs an additional .reloc > > pseudo-

[r12-1805 Regression] FAIL: gcc.dg/analyzer/setjmp-2.c (test for excess errors) on Linux/x86_64

2021-06-24 Thread sunil.k.pandey via Gcc-patches
On Linux/x86_64, e9e2bad7251477db92ab9ebcdc010f9282dd9890 is the first bad commit commit e9e2bad7251477db92ab9ebcdc010f9282dd9890 Author: Martin Sebor Date: Thu Jun 24 19:22:06 2021 -0600 middle-end: add support for per-location warning groups. caused FAIL: gcc.dg/analyzer/setjmp-2.c (te

Re: PING^1 [PATCH v4 0/2] x86: Convert CONST_WIDE_INT/CONST_VECTOR to broadcast

2021-06-24 Thread Hongtao Liu via Gcc-patches
I didn't receive https://gcc.gnu.org/pipermail/gcc-patches/2021-June/572436.html in my gmail account, does anyone know why? >--- a/gcc/config/i386/i386-protos.h >+++ b/gcc/config/i386/i386-protos.h >@@ -260,6 +260,7 @@ extern void ix86_expand_mul_widen_hilo (rtx, rtx, rtx, >bool, bool); > extern

Re: PING^1 [PATCH v4 0/2] x86: Convert CONST_WIDE_INT/CONST_VECTOR to broadcast

2021-06-24 Thread Hongtao Liu via Gcc-patches
On Fri, Jun 25, 2021 at 2:01 PM Hongtao Liu wrote: > > I didn't receive > https://gcc.gnu.org/pipermail/gcc-patches/2021-June/572436.html in my > gmail account, does anyone know why? > > > >--- a/gcc/config/i386/i386-protos.h > >+++ b/gcc/config/i386/i386-protos.h > >@@ -260,6 +260,7 @@ extern voi

Re: [PATCH 1/2] [i386] Fold blendv builtins into gimple.

2021-06-24 Thread Hongtao Liu via Gcc-patches
Hi: Ater a second thought, I gave up on refactoring blendv's pattern, we already have vec_mege with const_int mask, integer mask, and introducing vector mask doesn't look very good. Here is the final patch I'm going to check in. Fold __builtin_ia32_pblendvb128 (a, b, c) as VEC_COND_EXPR (c < 0

Re: [PATCH 2/2] [i386] For 128/256-bit vec_cond_expr, When mask operands is lt reg const0_rtx, blendv can be used instead of avx512 mask. [PR target/100648]

2021-06-24 Thread Hongtao Liu via Gcc-patches
On Mon, May 24, 2021 at 12:59 PM Hongtao Liu wrote: > > Hi: > This patch is about to add define_insn_and_split to convert avx512 > mask mov back to pblendv instructions when mask operand is (lt: reg > const0_rtx). > Hi: Here's the patch I'm going to check in. gcc/ChangeLog: PR target

Re: [PATCH][RFC] Add x86 subadd SLP pattern

2021-06-24 Thread Richard Biener
On Thu, 24 Jun 2021, Uros Bizjak wrote: > On Thu, Jun 24, 2021 at 1:07 PM Richard Biener wrote: > > > This addds SLP pattern recognition for the SSE3/AVX [v]addsubp{ds} v0, v1 > > instructions which compute { v0[0] - v1[0], v0[1], + v1[1], ... } > > thus subtract, add alternating on lanes, start

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