Re: [PATCH] assorted improvements for fold_truth_andor_1

On Sep 28, 2020, Richard Biener wrote: > On Fri, Sep 25, 2020 at 3:39 PM Alexandre Oliva wrote: >> This patch introduces various improvements to the logic that merges >> field compares. > Sorry for throwing a wrench in here but doing this kind of transform > during GENERIC folding is considere

Re: [Patch, Fortran] libgomp: Silence unpack's may be used uninitialized warning

Hi Damian, my silencing-a-warning patch is about warnings reported when compiling GCC itself. — There are also warning for internal/artificially created variables when compiling code with gfortran. This patch was about the former and I assume that you are seeing the later. But, otherwise, I conc

Re: Implement iterative dataflow in modref to track parameters

Hello. The patch caused: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97235 Martin

Re: [PATCH] Fix GCC 10+ build failure with zstd version 1.2.0 or older.

On Tue, Sep 29, 2020 at 2:46 AM Jim Wilson wrote: > > Extends the configure check for zstd.h to also verify the zstd version, > since gcc requires features that only exist in 1.3.0 and newer. Without > this patch we get a build error for lto-compress.c when using an old zstd > version. > > Tested

Re: [PATCH] assorted improvements for fold_truth_andor_1

On Tue, Sep 29, 2020 at 9:23 AM Alexandre Oliva wrote: > > On Sep 28, 2020, Richard Biener wrote: > > > On Fri, Sep 25, 2020 at 3:39 PM Alexandre Oliva wrote: > > >> This patch introduces various improvements to the logic that merges > >> field compares. > > > Sorry for throwing a wrench in here

Re: [PATCH] Add if-chain to switch conversion pass.

On Fri, Sep 25, 2020 at 4:05 PM Martin Liška wrote: > > On 9/24/20 2:41 PM, Richard Biener wrote: > > On Wed, Sep 2, 2020 at 1:53 PM Martin Liška wrote: > >> > >> On 9/1/20 4:50 PM, David Malcolm wrote: > >>> Hope this is constructive > >>> Dave > >> > >> Thank you David. All of them very very us

[PATCH][GCC 10] arm: Add support for Neoverse V1 CPU

Hello, This patch backports the AArch32 support for Arm's Neoverse V1 CPU to GCC 10. Testing: * Bootstrapped and regtested on arm-none-linux-gnueabihf. OK for GCC 10 branch? Thanks, Alex --- gcc/ChangeLog: * config/arm/arm-cpus.in (neoverse-v1): New. * config/arm/arm-tables.

Re: [PATCH] RISC-V: Define __riscv_cmodel_medany for PIC mode.

Thanks, committed with more comments in code :) On Tue, Sep 29, 2020 at 3:35 AM Jim Wilson wrote: > > On Thu, Sep 24, 2020 at 10:46 PM Kito Cheng wrote: > > > > - According the conclusion in RISC-V C API document, we decide to deprecat > >the __riscv_cmodel_pic marco > > > > - __riscv_cmod

RE: [PATCH][GCC 10] arm: Add support for Neoverse V1 CPU

> -Original Message- > From: Alex Coplan > Sent: 29 September 2020 09:59 > To: gcc-patches@gcc.gnu.org > Cc: ni...@redhat.com; Richard Earnshaw ; > Ramana Radhakrishnan ; Kyrylo > Tkachov > Subject: [PATCH][GCC 10] arm: Add support for Neoverse V1 CPU > > Hello, > > This patch backpor

Re: [PATCH v2 3/16]middle-end Add basic SLP pattern matching scaffolding.

Richard Biener writes: >> > > @@ -2192,6 +2378,17 @@ vect_analyze_slp_instance (vec_info *vinfo, >> > > &tree_size, bst_map); >> > >if (node != NULL) >> > > { >> > > + /* Temporarily allow add_stmt calls again. */ >> > > + vinfo->stmt_vec_info_ro =

Re: [PATCH v2 3/16]middle-end Add basic SLP pattern matching scaffolding.

On Tue, 29 Sep 2020, Richard Sandiford wrote: > Richard Biener writes: > >> > > @@ -2192,6 +2378,17 @@ vect_analyze_slp_instance (vec_info *vinfo, > >> > > &tree_size, bst_map); > >> > >if (node != NULL) > >> > > { > >> > > + /* Temporarily allow add_st

Re: [PATCH] libstdc++: Add C++2a synchronization support

On 28/09/20 14:29 -0700, Thomas Rodgers wrote: +template + __atomic_wait_status + __platform_wait_until_impl(__platform_wait_t* __addr, +__platform_wait_t __val, +const chrono::time_point<__platform_wait_clock_t, +

Re: [PATCH v2 6/16]middle-end Add Complex Addition with rotation detection

Tamar Christina writes: > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index > 2b46286943778e16d95b15def4299bcbf8db7eb8..71e226505b2619d10982b59a4ebbed73a70f29be > 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -6132,6 +6132,17 @@ floating-point mode. > > This pattern is not

Re: [PATCH, 1/3, OpenMP] Target mapping changes for OpenMP 5.0, front-end parts

On Tue, Sep 01, 2020 at 09:16:23PM +0800, Chung-Lin Tang wrote: > this patch set implements parts of the target mapping changes introduced > in OpenMP 5.0, mainly the attachment requirements for pointer-based > list items, and the clause ordering. > > The first patch here are the C/C++ front-end c

[PATCH][GCC 9] arm: Add support for Neoverse V1 CPU

Hello, This patch backports the AArch32 support for Arm's Neoverse V1 CPU to GCC 9. Testing: * Bootstrapped and regtested on arm-none-linux-gnueabihf. OK for GCC 9 branch? Thanks, Alex --- gcc/ChangeLog: * config/arm/arm-cpus.in (neoverse-v1): New. * config/arm/arm-tables.op

RE: [PATCH][GCC 9] arm: Add support for Neoverse V1 CPU

> -Original Message- > From: Alex Coplan > Sent: 29 September 2020 11:18 > To: gcc-patches@gcc.gnu.org > Cc: ni...@redhat.com; Richard Earnshaw ; > Ramana Radhakrishnan ; Kyrylo > Tkachov > Subject: [PATCH][GCC 9] arm: Add support for Neoverse V1 CPU > > Hello, > > This patch backport

aarch64/arm: GCC 10 backportx

I've backported the following SVE ACLE and stack-protector patches to GCC 10. The arm one was approved last week. Tested on aarch64-linux-gnu and arm-linux-gnueabihf. Richard >From 0559badf0176b257d3cba89f8eb4b08948216002 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 29 Sep 2020

[rs6000] Avoid useless masking of count operand for rotation

Hi, the Interfaces package of the Ada library defines a pair of rotation operators function Rotate_Left (Value : Unsigned_n; Amount : Natural) return Unsigned_n; function Rotate_Right (Value : Unsigned_n; Amount : Natural) return Unsigned_n; on modular (aka unsigned) types of

Ping: [PATCH] arm: Add new vector mode macros

Ping Richard Sandiford writes: > Kyrylo Tkachov writes: >> This looks like a productive way forward to me. >> Okay if the other maintainer don't object by the end of the week. > > Thanks. Dennis pointed out off-list that it regressed > armv8_2-fp16-arith-2.c, which was expecting FP16 vectorisat

Re: [PATCH] aarch64: Add extend-as-extract-with-shift pattern [PR96998]

Hi Segher, Gentle ping. Is the combine change (a canonicalization fix, as described below) OK for trunk in light of this info? On 22/09/2020 17:08, Richard Sandiford wrote: > Segher Boessenkool writes: > > Hi Alex, > > > > On Tue, Sep 22, 2020 at 08:40:07AM +0100, Alex Coplan wrote: > >> On 21/

RE: Ping: [PATCH] arm: Add new vector mode macros

> -Original Message- > From: Richard Sandiford > Sent: 29 September 2020 11:27 > To: Kyrylo Tkachov > Cc: gcc-patches@gcc.gnu.org; ni...@redhat.com; Richard Earnshaw > ; Ramana Radhakrishnan > ; Dennis Zhang > > Subject: Ping: [PATCH] arm: Add new vector mode macros > > Ping > > Ric

Re: [PATCH v2 6/16]middle-end Add Complex Addition with rotation detection

On Tue, 29 Sep 2020, Richard Sandiford wrote: > Tamar Christina writes: > > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > > index > > 2b46286943778e16d95b15def4299bcbf8db7eb8..71e226505b2619d10982b59a4ebbed73a70f29be > > 100644 > > --- a/gcc/doc/md.texi > > +++ b/gcc/doc/md.texi > > @@ -6132

Re: [PATCH 1/5] Don't enable -gvariable-location-views by default for DWARF5.

Hi, On Mon, 2020-08-24 at 19:38 +0200, Jakub Jelinek wrote: > On Mon, Aug 24, 2020 at 02:56:54PM +0200, Mark Wielaard wrote: > > DWARF5 makes it possible to read loclists tables without consulting > > the debuginfo tree by introducing a table header. Adding location > > views > > breaks this (at l

Re: [PATCH] c++: Diagnose visitors with different return types for std::visit [PR95904]

On 29/09/20 01:12 +0300, Ville Voutilainen via Libstdc++ wrote: Not completely tested yet. This does fix the problem of converting incompatible pointer-to-function types, and thus gets rid of the suggestion that compiling the code with -fpermissive is a possibility. There is a special-casing for

[PATCH] pass: Run cleanup passes before SLP [PR96789]

Hi, As the discussion in PR96789, we found that some scalar stmts which can be eliminated by some passes after SLP, but we still modeled their costs when trying to SLP, it could impact vectorizer's decision. One typical case is the case in PR on target Power. As Richard suggested there, this pat

Re: [committed] libstdc++: Use __libc_single_threaded to optimise atomics [PR 96817]

On Sat, 26 Sep 2020 at 21:42, Jonathan Wakely via Gcc-patches wrote: > > Glibc 2.32 adds a global variable that says whether the process is > single-threaded. We can use this to decide whether to elide atomic > operations, as a more precise and reliable indicator than > __gthread_active_p. > > Thi

Re: [PATCH] pass: Run cleanup passes before SLP [PR96789]

On Tue, Sep 29, 2020 at 1:30 PM Kewen.Lin wrote: > > Hi, > > As the discussion in PR96789, we found that some scalar stmts > which can be eliminated by some passes after SLP, but we still > modeled their costs when trying to SLP, it could impact > vectorizer's decision. One typical case is the ca

[PATCH][GCC 8] arm: Add support for Neoverse V1 CPU

Hello, This patch backports the AArch32 support for Arm's Neoverse V1 CPU to GCC 8. Testing: * Bootstrapped and regtested on arm-none-linux-gnueabihf. OK for GCC 8 branch? Thanks, Alex --- gcc/ChangeLog: * config/arm/arm-cpus.in (neoverse-v1): New. * config/arm/arm-tables.op

Re: [PATCH] Add type arg to TARGET_LIBC_HAS_FUNCTION

On 9/29/20 8:59 AM, Richard Biener wrote: > On Mon, Sep 28, 2020 at 7:28 PM Tom de Vries wrote: >> >> [ was: Re: [Patch][nvptx] return true in libc_has_function for >> function_sincos ] >> >> On 9/26/20 6:47 PM, Tobias Burnus wrote: >>> Found when looking at PR97203 (but having no effect there). >

[PATCH] tree-optimization/97238 - fix typo causing ICE

This fixes a typo causing a NULL dereference. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. 2020-09-29 Richard Biener PR tree-optimization/97238 * tree-ssa-reassoc.c (ovce_extract_ops): Fix typo. * gcc.dg/pr97238.c: New testcase. --- gcc/testsuite/gcc.

PING^3 [GCC 10] [PATCH] IRA: Don't make a global register eliminable

On Fri, Sep 25, 2020 at 6:46 AM H.J. Lu wrote: > > On Tue, Sep 22, 2020 at 10:48 AM H.J. Lu wrote: > > > > On Fri, Sep 18, 2020 at 10:21 AM H.J. Lu wrote: > > > > > > On Thu, Sep 17, 2020 at 3:52 PM Jeff Law wrote: > > > > > > > > > > > > On 9/16/20 8:46 AM, Richard Sandiford wrote: > > > > > >

[PATCH] move permute optimization to optimize-slp

This moves optimizing permutes of SLP reductions to vect_optimize_slp, eliding the global slp_loads array. Bootstrapped and tested on x86_64-unknown-linux-gnu, pushed. 2020-09-29 Richard Biener * tree-vect-slp.c (vect_analyze_slp): Move SLP reduction re-arrangement and SLP gra

[PATCH] Fortran : ICE in build_field PR95614 (2nd attempt)

For review. When the first attempt was committed the result was PR97224 i.e. it broke the build of SPECCPU 2006 Games. I've changed the condition under which the error is produced. It was produced in the local symbol was also found as a global symbol and the the type of the symbol was not GS

Re: [PATCH] pass: Run cleanup passes before SLP [PR96789]

Hi Richard, Thanks for the comments! > diff --git a/gcc/tree-ssa-loop-ivcanon.c b/gcc/tree-ssa-loop-ivcanon.c > index 298ab215530..7016f993339 100644 > --- a/gcc/tree-ssa-loop-ivcanon.c > +++ b/gcc/tree-ssa-loop-ivcanon.c > @@ -1605,6 +1605,14 @@ pass_complete_unroll::execute (function *fun) >

Re: [PATCH] assorted improvements for fold_truth_andor_1

On Sep 29, 2020, Richard Biener wrote: > On Tue, Sep 29, 2020 at 9:23 AM Alexandre Oliva wrote: >> On Sep 28, 2020, Richard Biener wrote: > ifcombine should stop using fold*, yeah Wow, that's quite a lot of work for no expected improvement in codegen. I don't expect to be able to justify suc

[PATCH] arm: Fix ICEs in no-literal-pool.c on MVE

Hello, This patch fixes ICEs when compiling gcc/testsuite/gcc.target/arm/pure-code/no-literal-pool.c with -mfp16-format=ieee -mfloat-abi=hard -march=armv8.1-m.main+mve -mpure-code. The existing conditions in the movsf/movdf expanders (as well as the no_literal_pool patterns) were too restrictive,

Re: Implement iterative dataflow in modref to track parameters

On 9/29/20 10:13 AM, Martin Liška wrote: Hello. The patch caused: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97235 Martin And these 2 PRs: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97243 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=97244 Thanks, Martin

Re: [PATCH] Fortran : Two further previously missed ICEs PR53298

On 16/09/2020 08:02, Andre Vehreschild wrote: Hi Mark, a few remarks: [...] [PATCH] Fortran  : Two further previously missed ICEs PR53298 There were 3 ICEs with different call stacks in the comments of this PR.  A previous commit fixed only one of those ICEs. The ICEs fixed here are in tr

Re: PING^3 [GCC 10] [PATCH] IRA: Don't make a global register eliminable

On 2020-09-29 8:38 a.m., H.J. Lu wrote: On Fri, Sep 25, 2020 at 6:46 AM H.J. Lu wrote: OK for GCC 10 branch? Thanks. PING: https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554268.html PING. PING. Sorry, I thought Jeff Law already approved this.  In any case the patch is also

RE: [PATCH][GCC 8] arm: Add support for Neoverse V1 CPU

> -Original Message- > From: Alex Coplan > Sent: 29 September 2020 13:17 > To: gcc-patches@gcc.gnu.org > Cc: ni...@redhat.com; Richard Earnshaw ; > Ramana Radhakrishnan ; Kyrylo > Tkachov > Subject: [PATCH][GCC 8] arm: Add support for Neoverse V1 CPU > > Hello, > > This patch backport

Re: BoF DWARF5 patches (25% .debug section size reduction)

On Thu, 2020-09-10 at 13:16 +0200, Jakub Jelinek wrote: > On Wed, Sep 09, 2020 at 09:57:54PM +0200, Mark Wielaard wrote: > > --- a/gcc/doc/invoke.texi > > +++ b/gcc/doc/invoke.texi > > @@ -9057,13 +9057,14 @@ possible. > > @opindex gdwarf > > Produce debugging information in DWARF format (if that

[PATCH] tree-optimization/97241 - fix ICE in reduction vectorization

The following moves an ad-hoc attempt at discovering the SLP node for a stmt to the place where we can find it in lock-step when we find the stmt itself. Bootstrapped / tested on x86_64-unknown-linux-gnu, pushed. 2020-09-29 Richard Biener PR tree-optimization/97241 * tree-vect

Fix internal fnspec

Hi, this patch fixes accidental \000 in fnspec strings for internal fns. OK? Honza * internal-fn.c (DEF_INTERNAL_FN): Fix call of build_string. diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c index 8ea3195d31c..c8970820026 100644 --- a/gcc/internal-fn.c +++ b/gcc/internal-fn.c @@ -93,7

Add trailing dots to fortran io fnspecs to match signature

Hi, this patch is not needed but makes it possible to sanity check that fnspec match function signature. It turns out that there are quite few mistakes in that in trans-decl and one mistake here. Transfer_derived has additional parameters. Bootstrapped/regtested x86_64-linux. OK? Honza *

[PATCH] c++: Set the constraints of a class type sooner [PR96229]

In the testcase below, during processing (at parse time) of Y's base class X, convert_template_argument calls is_compatible_template_arg to check if the template argument Y is no more constrained than the parameter P. But at this point we haven't yet set Y's constraints, so get_normalized_constrai

Re: Add trailing dots to fortran io fnspecs to match signature

On 9/29/20 4:20 PM, Jan Hubicka wrote: this patch is not needed but makes it possible to sanity check that fnspec match function signature. It turns out that there are quite few I'm sending the run-time sanity check patch and few more places that assert. I'm going to test the patch. Martin >Fr

[PATCH][GCC][AArch64] Add support for Cortex-X1

Hi, This change adds support for the Arm Cortex-X1 CPU in AArch64 GCC. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x OK for master branch ? kind regards, Przemyslaw Wirkus gcc/ChangeLog: * config/aarch64/aarch64-cores.def: Add Cortex-X

[PATCH][GCC][ARM] Add support for Cortex-X1

Hi, This change adds support for the Arm Cortex-X1 CPU. For more information about this processor, see [0]. [0] : https://www.arm.com/products/cortex-x OK for master branch ? kind regards, Przemyslaw Wirkus gcc/ChangeLog: * config/arm/arm-cpus.in: Add Cortex-X1 core.

Re: Add trailing dots to fortran io fnspecs to match signature

> On 9/29/20 4:20 PM, Jan Hubicka wrote: > > this patch is not needed but makes it possible to sanity check that > > fnspec match function signature. It turns out that there are quite few > > I'm sending the run-time sanity check patch and few more places that assert. > I'm going to test the patch

c++: Identifier type value should not update binding

This simplification removes some unneeded behaviour in set_identifier_type_value_with_scope, which was updating the namespace binding. And causing update_binding to have to deal with meeting two implicit typedefs. But the typedef is already there, and there's no other way to have two such typed

Re: Add trailing dots to fortran io fnspecs to match signature

On 9/29/20 4:45 PM, Jan Hubicka wrote: My fixup is longer:) Heh. So please include my gcc_checking_assert hunk to your patch. Martin All strings starting with R or W are wrong. However I have instances of miamatched lengths say for caf_register, deregister and others. There are few cases wh

Re: Fix internal fnspec

On September 29, 2020 4:17:30 PM GMT+02:00, Jan Hubicka wrote: >Hi, >this patch fixes accidental \000 in fnspec strings for internal fns. >OK? OK. Richard. >Honza > > * internal-fn.c (DEF_INTERNAL_FN): Fix call of build_string. >diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c >index

Re: Add trailing dots to fortran io fnspecs to match signature

On September 29, 2020 4:20:42 PM GMT+02:00, Jan Hubicka wrote: >Hi, >this patch is not needed but makes it possible to sanity check that >fnspec match function signature. It turns out that there are quite few >mistakes in that in trans-decl and one mistake here. >Transfer_derived has additional pa

[PATCH] i386: Define __LAHF_SAHF__ and __MOVBE__ macros, based on ISA flags

It looks like these have been omitted by accident. gcc/ * config/i386/i386-c.c (ix86_target_macros_internal): Define __LAHF_SAHF__ and __MOVBE__ based on ISA flags. --- gcc/config/i386/i386-c.c | 4 1 file changed, 4 insertions(+) diff --git a/gcc/config/i386/i386-c.c b/gcc

[PATCH][GCC 10] aarch64: Add support for Neoverse N2 CPU

Hello, This patch backports the AArch64 support for Arm's Neoverse N2 CPU to GCC 10. Testing: * Bootstrapped and regtested on aarch64-none-linux-gnu. OK for GCC 10 branch? Thanks, Alex --- gcc/ChangeLog: * config/aarch64/aarch64-cores.def: Add Neoverse N2. * config/aarch64/a

RE: [PATCH][GCC 10] aarch64: Add support for Neoverse N2 CPU

> -Original Message- > From: Alex Coplan > Sent: 29 September 2020 17:04 > To: gcc-patches@gcc.gnu.org > Cc: Richard Earnshaw ; Richard Sandiford > ; Kyrylo Tkachov > Subject: [PATCH][GCC 10] aarch64: Add support for Neoverse N2 CPU > > Hello, > > This patch backports the AArch64 supp

Re: [PATCH] assorted improvements for fold_truth_andor_1

On Sep 29, 2020, Alexandre Oliva wrote: > Yeah, ifcombine's bb_no_side_effects_p gives up on any gimple_vuse in > the inner block. that won't do when the whole point is to merge loads > from memory. > That seems excessive. Since we rule out any memory-changing side > effects, I suppose we coul

RE: [PATCH][GCC][AArch64] Add support for Cortex-X1

> -Original Message- > From: Przemyslaw Wirkus > Sent: 29 September 2020 15:39 > To: gcc-patches@gcc.gnu.org > Cc: Richard Earnshaw ; Richard Sandiford > ; Kyrylo Tkachov > ; Marcus Shawcroft > > Subject: [PATCH][GCC][AArch64] Add support for Cortex-X1 > > Hi, > > This change adds su

RE: [PATCH][GCC][ARM] Add support for Cortex-X1

From: Przemyslaw Wirkus Sent: 29 September 2020 15:43 To: gcc-patches@gcc.gnu.org Cc: ni...@redhat.com; Ramana Radhakrishnan ; Richard Earnshaw ; Kyrylo Tkachov Subject: [PATCH][GCC][ARM] Add support for Cortex-X1 Hi, This change adds support for the Arm Cortex-X1 CPU. For more informatio

RE: [PATCH] arm: Fix ICEs in no-literal-pool.c on MVE

Hi Alex, > -Original Message- > From: Alex Coplan > Sent: 29 September 2020 14:48 > To: gcc-patches@gcc.gnu.org > Cc: ni...@redhat.com; Richard Earnshaw ; > Ramana Radhakrishnan ; Kyrylo > Tkachov > Subject: [PATCH] arm: Fix ICEs in no-literal-pool.c on MVE > > Hello, > > This patch fi

Re: [PATCH] libstdc++: Diagnose visitors with different return types [PR95904]

On Tue, 29 Sep 2020 at 14:20, Jonathan Wakely wrote: > I think this is what we want: > >template > constexpr inline __same_types = (is_same_v<_Tp, _Types> && ...); > > is_same_v is very cheap, it uses the built-in directly, so you don't > need to instantiate any class templates at all. >

Re: Add trailing dots to fortran io fnspecs to match signature

> On September 29, 2020 4:20:42 PM GMT+02:00, Jan Hubicka > wrote: > >Hi, > >this patch is not needed but makes it possible to sanity check that > >fnspec match function signature. It turns out that there are quite few > >mistakes in that in trans-decl and one mistake here. > >Transfer_derived ha

c++: Name lookup simplifications

Here are a few cleanups, prior to landing the hidden decl changes. 1) Clear cxx_binding flags in the allocator, not at each user of the allocator. 2) Refactor update_binding. The logic was getting too convoluted. 3) Set friendliness and anticipatedness before pushing a template decl (not a

[SLP][VECT] Add check to fix 96837

Hi All, The following patch adds a simple check to prevent slp stmts from vector constructors being rearranged. vect_attempt_slp_rearrange_stmts tries to rearrange to avoid a load permutation. This fixes PR target/96837 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96827 gcc/ChangeLog: 2020-09

Re: [PATCH] Add Missing FSF copyright notes for some x86 intrinsic headers

On Mon, Sep 28, 2020 at 9:06 AM H.J. Lu wrote: > > On Mon, Sep 28, 2020 at 9:04 AM Hongyu Wang via Gcc-patches > wrote: > > > > Hi, > > > > Some x86 intrinsic headers is missing FSF copyright notes. This patch add > > the missed notes for those headers. > > > > OK for master? > > > > gcc/ChangeLo

[PATCH 6/6] ipa-cp: Separate and increase the large-unit parameter

A previous patch in the series has taught IPA-CP to identify the important cloning opportunities in 548.exchange2_r as worthwhile on their own, but the optimization is still prevented from taking place because of the overall unit-growh limit. This patches raises that limit so that it takes place a

[PATCH 0/6] IPA cleanups and IPA-CP improvements for 548.exchange2_r

Hi, this patch set is a result of rebasing the one I sent here three weeks ago on current trunk. Last week I also checked the WPA memory requirements when building Firefox and it did not change from the unpatched numbers. Bootstrapped and tested and LTO bootstrapped on x86-64. OK for trunk? Th

[PATCH 3/6] ipa: Bundle estimates of ipa_call_context::estimate_size_and_time

A subsequent patch adds another two estimates that the code in ipa_call_context::estimate_size_and_time computes, and the fact that the function has a special output parameter for each thing it computes would make it have just too many. Therefore, this patch collapses all those ouptut parameters i

[PATCH 4/6] ipa: Multiple predicates for loop properties, with frequencies

This patch enhances the ability of IPA to reason under what conditions loops in a function have known iteration counts or strides because it replaces single predicates which currently hold conjunction of predicates for all loops with vectors capable of holding multiple predicates, each with a cumul

[PATCH 2/6] ipa: Introduce ipa_cached_call_context

Hi, as we discussed with Honza on the mailin glist last week, making cached call context structure distinct from the normal one may make it clearer that the cached data need to be explicitely deallocated. This patch does that division. It is not mandatory for the overall main goals of the patch

[PATCH 1/6] ipa: Bundle vectors describing argument values

Hi, this large patch is mostly mechanical change which aims to replace uses of separate vectors about known scalar values (usually called known_vals or known_csts), known aggregate values (known_aggs), known virtual call contexts (known_contexts) and known value ranges (known_value_ranges) with us

[PATCH 5/6] ipa-cp: Add dumping of overall_size after cloning

When experimenting with IPA-CP parameters, especially when looking into exchange2_r, it has been very useful to know what the value of overall_size is at different stages of the decision process. This patch therefore adds it to the generated dumps. gcc/ChangeLog: 2020-09-07 Martin Jambor

Re: [PATCH 2/6] ipa: Introduce ipa_cached_call_context

> Hi, > > as we discussed with Honza on the mailin glist last week, making > cached call context structure distinct from the normal one may make it > clearer that the cached data need to be explicitely deallocated. > > This patch does that division. It is not mandatory for the overall > main goa

Re: [PATCH 3/6] ipa: Bundle estimates of ipa_call_context::estimate_size_and_time

> A subsequent patch adds another two estimates that the code in > ipa_call_context::estimate_size_and_time computes, and the fact that > the function has a special output parameter for each thing it computes > would make it have just too many. Therefore, this patch collapses all > those ouptut pa

Re: [PATCH 5/6] ipa-cp: Add dumping of overall_size after cloning

> When experimenting with IPA-CP parameters, especially when looking > into exchange2_r, it has been very useful to know what the value of > overall_size is at different stages of the decision process. This > patch therefore adds it to the generated dumps. > > gcc/ChangeLog: > > 2020-09-07 Mart

[PATCH] x86: Replace with

Fix a typo in config/i386/enqcmdintrin.h by replacing with : [hjl@gnu-cfl-2 x86-gcc]$ echo "#include " | gcc -S -o /dev/null -x c - In file included from :1: /usr/lib/gcc/x86_64-redhat-linux/10/include/enqcmdintrin.h:25:3: error: #error "Never use directly; include instead." 25 | # error "

Re: [PATCH] x86: Replace with

On Tue, Sep 29, 2020 at 11:46:24AM -0700, H.J. Lu via Gcc-patches wrote: > Fix a typo in config/i386/enqcmdintrin.h by replacing > with : > > [hjl@gnu-cfl-2 x86-gcc]$ echo "#include " | gcc -S -o > /dev/null -x c - > In file included from :1: > /usr/lib/gcc/x86_64-redhat-linux/10/include/enqcmdi

V2 [PATCH] x86: Replace with

On Tue, Sep 29, 2020 at 11:49 AM Jakub Jelinek wrote: > > On Tue, Sep 29, 2020 at 11:46:24AM -0700, H.J. Lu via Gcc-patches wrote: > > Fix a typo in config/i386/enqcmdintrin.h by replacing > > with : > > > > [hjl@gnu-cfl-2 x86-gcc]$ echo "#include " | gcc -S -o > > /dev/null -x c - > > In file i

Re: V2 [PATCH] x86: Replace with

On Tue, Sep 29, 2020 at 11:58:39AM -0700, H.J. Lu wrote: > Here is the V2 patch. OK for master and GCC 10 branches? Yes, thanks. Jakub

Re: [rs6000] Avoid useless masking of count operand for rotation

Hi! [ Please CC: me on rs6000 patches. Thanks! ] On Tue, Sep 29, 2020 at 12:26:28PM +0200, Eric Botcazou wrote: > and the masking is present all the way down to the assembly at -O2: > > rlwinm 4,4,0,27,31 > rotlw 3,3,4 > > Now this masking is redundant since it's done by the ha

Re: [PATCH] aarch64: Add extend-as-extract-with-shift pattern [PR96998]

On Tue, Sep 29, 2020 at 11:36:12AM +0100, Alex Coplan wrote: > Is the combine change (a canonicalization fix, as described below) OK > for trunk in light of this info? Can you please resend it with correct info and a corresponding commit message? Segher

c++: Hiddenness is a property of the symbol table

This patch moves the handling of decl-hiddenness entirely into the name lookup machinery, where it belongs. We need a few new flags, because pressing the existing OVL_HIDDEN_P into play for non-function decls doesn't work well. For a local binding we only need one marker, as there cannot be both

[PATCH] libgomp: Enforce 1-thread limit in subteams

My recent patch to fix barriers in nested teams relied on the assumption that nested teams would only ever have one thread each. However, that can be changed by altering the ICVs, via runtime call or environment variable (not that the accelerator-side libgomp can see the host environment), so

Re: [PATCH 6/6] ipa-cp: Separate and increase the large-unit parameter

> > gcc/ChangeLog: > > 2020-09-07 Martin Jambor > > * params.opt (ipa-cp-large-unit-insns): New parameter. > * ipa-cp.c (get_max_overall_size): Use the new parameter. OK, thanks! Honza > --- > gcc/ipa-cp.c | 2 +- > gcc/params.opt | 4 > 2 files changed, 5 insertions(+), 1

[PATCH] arm: Fix multiple inheritance thunks for thumb-1 with -mpure-code

When mi_delta is > 255 and -mpure-code is used, we cannot load delta from code memory (like we do without -mpure-code). This patch builds the value of mi_delta into r3 with a series of movs/adds/lsls. We also do some cleanup by not emitting the function address and delta via .word directives at t

Another issue on RS6000 target. Re: One issue with default implementation of zero_call_used_regs

Hi, Richard, At the same time testing aarch64, I also tested the default implementation on rs6000 target. The default implementation now is: +/* The default hook for TARGET_ZERO_CALL_USED_REGS. */ + +HARD_REG_SET +default_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs) +{ + gcc_asser

Re: [PATCH] c++: CTAD and explicit deduction guides for copy-list-init [PR90210]

Ping. On Sat, Sep 19, 2020 at 05:33:36PM -0400, Marek Polacek via Gcc-patches wrote: > This PR points out that we accept > > template struct tuple { tuple(T); }; // #1 > template explicit tuple(T t) -> tuple; // #2 > tuple t = { 1 }; > > despite the 'explicit' deduction guide in a copy-lis

Re: [PATCH] c++: Fix P0846 (ADL and function templates) in template [PR97010]

Ping. On Fri, Sep 18, 2020 at 04:05:16PM -0400, Marek Polacek via Gcc-patches wrote: > Ping. > > On Thu, Sep 10, 2020 at 06:15:24PM -0400, Marek Polacek via Gcc-patches wrote: > > To quickly recap, P0846 says that a name is also considered to refer to > > a template if it is an unqualified-id fol

Re: [PATCH] c++: Implement -Wrange-loop-construct [PR94695]

On 9/28/20 11:34 AM, Marek Polacek wrote: On Fri, Sep 25, 2020 at 04:31:16PM -0600, Martin Sebor wrote: On 9/24/20 6:05 PM, Marek Polacek via Gcc-patches wrote: This new warning can be used to prevent expensive copies inside range-based for-loops, for instance: struct S { char arr[128]; };

[committed] analyzer: silence -Wsign-compare warnings

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to master as 9b4b1ed50f1e0f252a86851456b58bb2e142c495. gcc/analyzer/ChangeLog: * constraint-manager.cc (constraint_manager::add_constraint_internal): Whitespace fixes. Silence -Wsign-compare warning.

[PATCH] c++: ICE in dependent_type_p with constrained auto [PR97052]

This patch fixes an "unguarded" call to coerce_template_parms in build_standard_check: processing_template_decl could be zero if we we get here during processing of the first 'auto' parameter of an abbreviated function template. In the testcase below, this leads to an ICE when coerce_template_parm

[PATCH] avoid modifying type in place (PR 97206)

To render the bounds as well as the static specifier in array and VLA function parameters the new -Warray-parameter and -Wvla-parameter warning builds a "synthetic" array type that corresponds to the form of the parameter, sets its qualifiers to match those of the pointer, and passes it to the pr

RE: [PATCH][GCC][AArch64] Add support for Cortex-X1

> Ok. Please make sure aarch64-tune.md is properly regenerated when > committing as Alex has been adding new CPUs in there recently too. commit f836f3bc8f76ef3e3ad21762590302ad11abc9f8 > Thanks, > Kyrill > > > > > kind regards, > > Przemyslaw Wirkus > > > > gcc/ChangeLog: > > > > * config/aarch6

RE: [PATCH][GCC][ARM] Add support for Cortex-X1

> Ok, but please make sure this is properly rebased on top of Alex's patches > that have recently gone in in this area. commit 0eef5eea2b42d892df52b655e55458f27ac3fb81 > Thanks, > Kyrill > > > kind regards, > Przemyslaw Wirkus > > gcc/ChangeLog: > >   * config/arm/arm-cpus.in: Add

Re: [PATCH 4/6] ipa: Multiple predicates for loop properties, with frequencies

> This patch enhances the ability of IPA to reason under what conditions > loops in a function have known iteration counts or strides because it > replaces single predicates which currently hold conjunction of > predicates for all loops with vectors capable of holding multiple > predicates, each wi

[committed] analyzer: fix signal-handler registration location [PR95188]

PR analyzer/95188 reports that diagnostics from -Wanalyzer-unsafe-call-within-signal-handler use the wrong source location when reporting the signal-handler registration event in the diagnostic_path. The diagnostics erroneously use the location of the first stmt in the basic block containing the c

Re: [PATCH v3] c++: Implement -Wrange-loop-construct [PR94695]

On Mon, Sep 28, 2020 at 03:05:55PM -0400, Jason Merrill via Gcc-patches wrote: > On 9/28/20 12:30 PM, Marek Polacek wrote: > > On Sat, Sep 26, 2020 at 01:22:41AM -0400, Jason Merrill wrote: > > > > +bool > > > > +ref_conv_binds_directly_p (tree type, tree expr) > > > > +{ > > > > + gcc_assert (TYP

[pushed] correct/improve handling of null VLA arguments (PR 97188)

I have committed & pushed the fix in r11-3540. On 9/24/20 6:15 PM, Martin Sebor wrote: The machinery recently added to support -Warray-parameter and -Wvla-parameter also results in enhanced detection of null pointer arguments to VLA function parameters.  This enhancement wasn't tested as compreh

Re: [PATCH v2] builtins: (not just) rs6000: Add builtins for fegetround, feclearexcept and feraiseexcept [PR94193]

Hi Raoni, Some of this isn't an rs6000 patch, but the subject says it is, so it might well not draw the attention it needs. Adding some Cc:s. On Fri, Sep 04, 2020 at 12:52:30PM -0300, Raoni Fassina Firmino wrote: > There is one pending question raised by Segher, It is about adding > documentatio

[PATCH] rs6000: Use parameterized names for tablejump

We have too many tablejump patterns. Using parameterized names simplifies the code a bit. Tested on powerpc64-linux {-m32,-m64}. Committing. Segher 2020-09-29 Segher Boessenkool * config/rs6000/rs6000.md (tablejump): Simplify. (tablejumpsi): Merge this ... (tablej

  1   2   >