[PATCH 2/5] RS6000 add 128-bit Integer Operations

Will, Segher: Add support for divide, modulo, shift, compare of 128-bit integers instructions and builtin support. The following are the changes from the previous version of the patch. The TARGET_TI_VECTOR_OPS was removed per comments for patch 3. Just using TARGET_POWER10. Removed extra com

[PATCH 5/5] Conversions between 128-bit integer and floating point values.

Segher, Will: Patch 5 adds the 128-bit integer to/from 128-floating point conversions. This patch has to invoke the routines to use the 128-bit hardware instructions if on Power 10 or use software routines if running on a pre Power 10 system via the resolve function. Add ifunc resolves for __f

[PATCH 4/5] Test 128-bit shifts for just the int128 type.

Segher, Will: Patch 4 adds the vector 128-bit integer shift instruction support for the V1TI type. The following changes were made from the previous version. Renamed VSX_TI to VEC_TI, put def in vector.md. Didn't get it separated into a different patch. Reworked the XXSWAPD_V1TI to not use U

PR97107, libgo fails to build for power10

Calls from split-stack code to non-split-stack code need to expand mapped stack memory via __morestack. Even tail calls. __morestack is quite a surprising function on powerpc in that it calls back to its caller, and a tail call will continue running in the context of extra mapped stack. Bootstra

Re: PING [Patch][Middle-end]Add -fzero-call-used-regs=[skip|used-gpr|all-gpr|used|all]

On Mon, Sep 21, 2020 at 03:58:25PM -0500, Qing Zhao wrote: > > On Sep 21, 2020, at 3:34 PM, Segher Boessenkool > > wrote: > > But you cannot *add* anything with this interface, and it cannot return > > different results depending on which return insn this is. It is not a > > good abstraction IMO

[RS6000] Power10 libffi fixes

Power10 pc-relative code doesn't use or preserve r2 as a TOC pointer. That means calling between pc-relative and TOC using code can't be done without intervening linker stubs, and a call from TOC code to pc-relative code must have a nop after the bl in order to restore r2. Now the PowerPC libffi a

Re: Do we need to do a loop invariant motion after loop interchange ?

Bin, I just tested your patch on current trunk.  Here is my summary. 1. About some iv aren't moved out of inner loop (Lijia mentioned in his last email)   [local count: 955630226]:   # l_32 = PHI <1(12), l_54(21)>   # ivtmp_165 = PHI <_446(12), ivtmp_155(21)>   _26 = (integer(kind=8)) l_32;  

Ping: [PATCH 0/3] Power10 PCREL_OPT support (September 5th 2020)

In case this patch has gotten over-looked, the three patches in the set plus the explanation are the rewrite of the PCREL_OPT patches. It has been rewritten to use the data flow machinery as well as validate_change and apply_change_group from the last patch. The PCREL_OPT patches can go anywhere

Re: [PATCH] vect/test: Don't check for epilogue loop [PR97075]

Hi Richard, on 2020/9/21 下午2:50, Richard Sandiford wrote: > "Kewen.Lin" writes: >> Hi Richard, >>> "Kewen.Lin" writes: Hi, The commit r11-3230 brings a nice improvement to use full vectors instead of partial vectors when available. But it caused some vector with length

[PATCH 0/2] Rework adding Power10 IEEE 128-bit min, max, and conditional move

These patches are my latest versions of the patches to add IEEE 128-bit min, max, and conditional move to GCC. They correspond to the earlier patches #3 and #4 (patches #1 and #2 have been installed). The first patch just adds support for the xsmincqp and xsmaxcqp instructions. Due to the NaN rul

[PATCH 1/2] Power10: Add IEEE 128-bit xsmaxcqp and xsmincqp support.

Power10: Add IEEE 128-bit xsmaxcqp and xsmincqp support. This patch adds the support for the IEEE 128-bit floating point C minimum and maximum instructions. The next patch will add the support for using the compare and set mask instruction to implement conditional moves. Rather than trying to ov

[PATCH 2/2] Power10: Add IEEE 128-bit fp conditional move

Power10: Add IEEE 128-bit fp conditional move. This patch adds the support for power10 IEEE 128-bit floating point conditional move and for automatically generating min/max. Unlike the previous patch, I decided to keep two separate patterns for fpmask before splitting (one pattern for normal comp

[PATCH v3 1/2] IFN: Implement IFN_VEC_SET for ARRAY_REF with VIEW_CONVERT_EXPR

Thanks for the review, On 2020/9/21 16:31, Richard Biener wrote: + +static gimple * +gimple_expand_vec_set_expr (gimple_stmt_iterator *gsi) +{ + enum tree_code code; + gcall *new_stmt = NULL; + gassign *ass_stmt = NULL; + + /* Only consider code == GIMPLE_ASSIGN. */ + gassign *stmt = dyn_

[RFC] update COUNTs of BB in loop.

Hi, When investigating the issue from https://gcc.gnu.org/pipermail/gcc-patches/2020-July/549786.html I find the BB COUNTs of loop seems are not accurate in some case. For example: In below figure: COUNT:268435456 pre-header | |

Re: New modref/ipa_modref optimization passes

> On Sun, 2020-09-20 at 19:30 +0200, Jan Hubicka wrote: > > > On Sun, 2020-09-20 at 00:32 +0200, Jan Hubicka wrote: > > > > Hi, > > > > this is cleaned up version of the patch. I removed unfinished > > > > bits, > > > > fixed > > > > propagation, cleaned it up and fixed fallout. > > > > > > [...]

<    1   2