libgo patch committed: Add -maix32 when calling GCC on 32-bit AIX

This libgo patch by Clément Chigot adds -maix32 when running GCC on 32-bit AIX. As gcc might now be compiled in 64bit, -maix32 must always be added to ensure that created objects will be 32bit. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian 0c223b02b6e4dfbde

Re: Duplicate .debug_lines (Was: [PATCH 5/5] Add --gdwarf-5 to ASM_SPEC)

On Wed, Aug 26, 2020 at 2:38 PM Mark Wielaard wrote: > > Hi gcc hackers, binutils hackers, > > Nick, Jakub and I were discussing the gcc patch below and all the ways > it is wrong. Most things can be fixed in the spec. Like only passing > -gdwarf if we are generating DWARF and passing the right DW

Re: [PATCH] hppa: Improve expansion of ashldi3 when !TARGET_64BIT

On 2020-08-26 5:23 p.m., Roger Sayle wrote: > These more accurate target rtx_costs are used by the > gimple-ssa-strength-reduction.c > (via a call to mult_by_coeff_cost) to decide whether applying strength > reduction would > be profitable. This test case, slsr-13.c, assumes that two multiplicat

[PATCH] testsuite: add -fno-tree-fre in gcc.dg/guality

This patch add -fno-tree-fre to dg-options in gcc.dg/guality/sra-1.c, to make the following testcases passed. FAIL: gcc.dg/guality/sra-1.c -Og -DPREVENT_OPTIMIZATION line 43 a.i == 4 FAIL: gcc.dg/guality/sra-1.c -Og -DPREVENT_OPTIMIZATION line 43 a.j == 14 FAIL: gcc.dg/guality/s

Re: [PATCH] lra: Canonicalize mult to shift in address reloads

On 2020-08-26 11:15 a.m., Alex Coplan wrote: Thanks for the review, both. Please find a reworked version of the patch attached incorporating Richard's feedback. Testing: * Bootstrap and regtest on aarch64-none-linux-gnu, arm-none-linux-gnueabihf, and x86_64-pc-linux-gnu: no regressions.

[PATCH] Add power10 IEEE 128-bit minimum, maximum, and compare with mask instructions

The following patches are a rewrite of the previous set of patches to add support for the power10 IEEE 128-bit C minimum, C maximum, and compare/set mask instructions that are similar to the instructions added in power9. There are 4 patches in this series. The first patch is a cosmetic patch. In

[PATCH 1/4] PowerPC: Change cmove function return to bool

PowerPC: Change cmove function return to bool. In doing the other work for adding ISA 3.1 128-bit minimum, maximum, and conditional move support, I noticed the two functions that process conditional moves return 'int' instead of 'bool'. This patch changes these functions to return 'bool'. I have

[PATCH 2/4] PowerPC: Rename functions for min, max, cmove

PowerPC: Rename functions for min, max, cmove. This patch renames the functions that generate the ISA 3.0 C minimum, C maximum, and conditional move instructions to use a better name than just using a _p9 suffix. Because the functions can fail, the names use "maybe_emit" instead of "generate_" in

[PATCH 3/4] PowerPC: Add power10 xsmaxcqp/xsmincqp support

PowerPC: Add power10 xsmaxcqp/xsmincqp support. This patch adds support for the ISA 3.1 (power10) IEEE 128-bit "C" minimum and maximum functions. Because of the NaN differences, the built-in functions will only generate these instructions if -ffast-math is used until the conditional move support

[PATCH 4/4] PowerPC: Add power10 xscmp{eq,gt,ge}qp support

PowerPC: Add power10 xscmp{eq,gt,ge}qp support. This patch adds the conditional move support. In adding the conditional move support, the optimizers will be able to convert things like: a = (b > c) ? b : c; into the instructions. This patch merges together the scalar SF/DF conditional

RE: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions emitted at -O3

> -Original Message- > From: Richard Sandiford [mailto:richard.sandif...@arm.com] > Sent: Wednesday, August 26, 2020 6:14 PM > To: xiezhiheng > Cc: Richard Biener ; gcc-patches@gcc.gnu.org > Subject: Re: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions > emitted at -O3 > Cut...

RE: [PATCH] fix testcase gcc.target/aarch64/insv_1.c

Hi Richard I found that some instructions are using '#' before immediate value， and others are not. For example (define_insn "insv_imm" [(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r") (const_int 16) (match_operand:GPI 1 "c

[Patch, fortran] PR96624 - A segment fault occurred when using the reshape function result to assign a variable

Hi All, Here is another of Steve Kargl's patches. Before the patch is applied, the following code is generated: atmp.0.span = 4; atmp.0.data = 0B; atmp.0.offset = 0; (*(integer(kind=4)[0] * restrict) atmp.0.data)[0] = 1; (*(integer(kind=4)[0] * restrict) atmp.0.data)[1] = 2;

<    1   2