Re: [PATCH 4/4][PR target/88808]Enable bitwise operator for AVX512 masks.

On Wed, Aug 19, 2020 at 4:25 AM Hongtao Liu wrote: > > On Mon, Aug 17, 2020 at 6:08 PM Uros Bizjak wrote: > > > > On Fri, Aug 14, 2020 at 10:26 AM Hongtao Liu wrote: > > > > > > Enable operator or/xor/and/andn/not for mask register, kxnor is not > > > enabled since there's no corresponding instr

Re: [PATCH V2] libgccjit: Add new gcc_jit_context_new_blob entry point

David Malcolm writes: > Thanks for the updated patch. Comments inline below. Hi Dave, sorry for the late reply. > [...] > >> diff --git a/gcc/jit/docs/topics/expressions.rst >> b/gcc/jit/docs/topics/expressions.rst >> index d783ceea51a8..7699dcfd27be 100644 >> --- a/gcc/jit/docs/topics/expre

[PATCH] libgccjit: update some comments in libgccjit.c

Hi all, just a small patch updating some comments that apparently went out of sync a while ago adding gcc_jit_context_new_rvalue_from_long. Okay for trunk? Thanks Andrea >From 84b94a039d164878bdbf8bfd1a2038960f813c76 Mon Sep 17 00:00:00 2001 From: Andrea Corallo Date: Thu, 6 Aug 2020 10:25:

[RISC-V] Add support for AddressSanitizer on RISC-V GCC

From: cooper.joshua gcc/ * config/riscv/riscv.c (asan_shadow_offset): Implement the offset of asan shadow memory for risc-v. (asan_shadow_offset): new macro definition. --- gcc/config/riscv/riscv.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/gcc/co

RE: [PATCH] aarch64: Don't generate invalid zero/sign-extend syntax

Hi Richard, > -Original Message- > From: Richard Sandiford > Sent: 18 August 2020 09:35 > To: Alex Coplan > Cc: gcc-patches@gcc.gnu.org; Richard Earnshaw ; > Marcus Shawcroft ; Kyrylo Tkachov > > Subject: Re: [PATCH] aarch64: Don't generate invalid zero/sign-extend > syntax > > Alex Co

Re: [RISC-V] Add support for AddressSanitizer on RISC-V GCC

I'm having trouble understanding why different ports chose their various constants--e.g., SPARC uses 1<<29 for 32-bit and 1<<43 for 64-bit, whereas x86 uses 1<<29 and 0x7fff8000, respectively. So I can't comment on the choice of the constant 1<<36 for RISC-V. But isn't it a problem that 1<<36 is

Re: [PATCH] testsuite: require c99 runtime for trigonometric optimisation tests

Pat Bernardi writes: > A number of optimisation that simplify trigonometric expressions are only > performed when the compiler knows the target has a C99 libm available. > Since targets like *-elf may not have such a libm, a C99 runtime requirement > is added to these tests. > > Tested on x86-elf

Re: [PATCH 1/2] Add new RTX instruction class FILLER_INSN

Segher Boessenkool writes: > Hi Andrea, > > On Wed, Jul 22, 2020 at 12:02:33PM +0200, Andrea Corallo wrote: >> This first patch implements the addition of a new RTX instruction class >> FILLER_INSN, which has been white listed to allow placement of NOPs >> outside of a basic block. This is to al

[PATCH V2] Add pattern for pointer-diff on addresses with same base/offset (PR 94234)

As Richard's comment, this patch is composed to simplify generalized binary-with-convert pattern like ((T) X) OP ((T) Y). Instead of creating almost duplicated rules into match.pd, we try to transform it to (T) (X OP Y), and apply simplification on (X OP Y) in forwprop pass. Regards, Feng --- 2020

Re: [RISC-V] Add support for AddressSanitizer on RISC-V GCC

Hi Andrew: I am not sure the reason why some targets pick different numbers. It seems it's not only target dependent but also OS dependent[1]. For RV32, I think using 1<<29 like other 32 bit targets is fine. [1] https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/asan/asan_mapping.

[PATCH] arm: Fix -mpure-code support/-mslow-flash-data for armv8-m.base [PR94538]

armv8-m.base (cortex-m23) has the movt instruction, so we need to disable the define_split to generate a constant in this case, otherwise we get incorrect insn constraints as described in PR94538. We also need to fix the pure-code alternative for thumb1_movsi_insn because the assembler complains w

RE: [PATCH] AArch64: Add if condition in aarch64_function_value [PR96479]

Hi Richard, Thanks for the example. I remove the whole line "&&fndecl && TREE_PUBLIC (fndecl)" and passed bootstrap and deja tests. I add your provided example under /gcc.target/aarch64, and the patch is attached. By the way, the new example also passed deja tests. All the best, Peixin -

Re: [PATCH] libstdc++: Implement integer-class types as defined in [iterator.concept.winc]

On 11/08/20 11:38 -0400, Patrick Palka via Libstdc++ wrote: Subject: [PATCH] libstdc++: integer-class types as per [iterator.concept.winc] This implements signed and unsigned integer-class types, whose width is one bit larger than the widest supported signed and unsigned integral type respective

Re: [PATCH] AArch64: Add if condition in aarch64_function_value [PR96479]

qiaopeixin writes: > Hi Richard, > > Thanks for the example. > > I remove the whole line "&&fndecl && TREE_PUBLIC (fndecl)" and passed > bootstrap and deja tests. I add your provided example under > /gcc.target/aarch64, and the patch is attached. Thanks, pushed to master. Richard

Re: [PATCH PR94442] [AArch64] Redundant ldp/stp instructions emitted at -O3

xiezhiheng writes: > I add FLAGS for part of intrinsics in aarch64-simd-builtins.def first for a > try, > including all the add/sub arithmetic intrinsics. > > Something like faddp intrinsic which only handles floating-point operations, > both FP and NONE flags are suitable for it because FLAG_FP

Re: [PATCH PR96357][GCC][AArch64]: could not split insn UNSPEC_COND_FSUB with AArch64 SVE

Przemyslaw Wirkus writes: > Hi, > > Problem is related to that operand 4 (In original pattern > *cond_sub_any_const) is no longer the same as operand 1, and so > the pattern doesn't match the split condition. > > Pattern *cond_sub_any_const is being split by this patch into two > separate patterns

RE: [PATCH] AArch64: Add if condition in aarch64_function_value [PR96479]

Thanks. All the best, Peixin -Original Message- From: Richard Sandiford [mailto:richard.sandif...@arm.com] Sent: Wednesday, August 19, 2020 5:56 PM To: qiaopeixin Cc: Christophe Lyon ; gcc-patches@gcc.gnu.org Subject: Re: [PATCH] AArch64: Add if condition in aarch64_function_value [PR9

Re: [PATCH] x86: Detect Rocket Lake and Alder Lake

Hello, On 16 авг 06:17, H.J. Lu via Gcc-patches wrote: > From arch/x86/include/asm/intel-family.h on Linux kernel master branch: > > #define INTEL_FAM6_ROCKETLAKE 0xA7 > #define INTEL_FAM6_ALDERLAKE0x97 > > * common/config/i386/cpuinfo.h (get_intel_cpu): Detect Rock

Re: [PATCH] libibery/hashtab: add new functions

On 8/18/20 1:38 AM, Ian Lance Taylor wrote: I guess I'm not sure why either of these belong in libiberty. htab_insert can be written elsewhere as needed. And while perhaps some sort of stats API would be reasonable, I don't think it should be something that prints values to a FILE. Understood.

Re: [PATCH 1/2] Add new RTX instruction class FILLER_INSN

Andrea Corallo writes: > Segher Boessenkool writes: > >> Hi Andrea, >> >> On Wed, Jul 22, 2020 at 12:02:33PM +0200, Andrea Corallo wrote: >>> This first patch implements the addition of a new RTX instruction class >>> FILLER_INSN, which has been white listed to allow placement of NOPs >>> outside

Re: [PATCH] cmpelim: recognize extra clobbers in insns

Sorry for the slow reply. Pip Cet via Gcc-patches writes: > I'm working on the AVR cc0 -> CCmode conversion (bug#92729). One > problem is that the cmpelim pass is currently very strict in requiring > insns of the form > > (parallel [(set (reg:SI) (op:SI ... ...)) >(clobber (reg:CC REG

Re: [PATCH] PR target/96347: non-delegitimized UNSPEC UNSPEC_TP (19) found in variable location

Iain Buclaw via Gcc-patches writes: > Hi, > > On x86, a memory reference reference to a TLS address can be broken out > and stored in a register, for instance: > > movq %fs:8+testYearsBC@tpoff, %rdx > > Subsequently becomes: > > pushq %rbp > leaq 8+testYearsBC@tpoff, %rbp

Re: [PATCH] Using gen_int_mode instead of GEN_INT to avoid ICE caused by type promotion.

ping ^ 4, it's a very simple fix for ICE. On Mon, Aug 10, 2020 at 6:00 PM Hongtao Liu wrote: > > Ping^3 > > On Tue, Aug 4, 2020 at 4:21 PM Hongtao Liu wrote: > > > > ping ^2 > > > > On Mon, Jul 27, 2020 at 5:31 PM Hongtao Liu wrote: > > > > > > ping > > > > > > On Wed, Jul 22, 2020 at 3:57 PM H

Re: [PATCH] PR libstdc++/71579 assert that type traits are not misused with an incomplete type

On 12/08/20 11:19 +0300, Antony Polukhin via Libstdc++ wrote: Fixed patch for type traits hardening Changelog 2020-08-12 Antony Polukhin PR libstdc/71579 * include/std/type_traits (invoke_result, is_nothrow_invocable_r) Add static_asserts to make sure that the argument of the type

[committed] libstdc++: Add deprecated attributes to old iostream members

Back in 2017 I removed these prehistoric members (which were deprecated since C++98) for C++17 mode. But I didn't add deprecated attributes to most of them, so users didn't get any warning they would be going away. Apparently some poor souls do actually use some of these names, and so now that GCC

Re: [PATCH] [AVX512]For vector compare to mask register, UNSPEC is needed instead of comparison operator [PR96243]

ping^1 On Tue, Aug 11, 2020 at 5:43 PM Hongtao Liu wrote: > > Hi: > The issue is described in the bugzilla. > Bootstrap is ok, regression test for i386/x86-64 backend is ok. > Ok for trunk? > > ChangeLog > gcc/ > PR target/96551 > * config/i386/sse.md (vec_unpacku_float_hi_v1

Re: [PATCH] bb-reorder: Remove a misfiring micro-optimization (PR96475)

Segher Boessenkool writes: > When the compgotos pass copies the tail of blocks ending in an indirect > jump, there is a micro-optimization to not copy the last one, since the > original block will then just be deleted. This does not work properly > if cleanup_cfg does not merge all pairs of block

Re: [PATCH] vxworks: Fix GCC selftests for *-wrs-vxworks7-* targets

Excerpts from Olivier Hainque's message of August 18, 2020 2:25 pm: > Hi Iain, > >> On 18 Aug 2020, at 13:45, Iain Buclaw wrote: >> >> Attached is the change as per your proposal. >> >> * config/vxworks.h (VXWORKS_ADDITIONAL_CPP_SPEC): Replace -nostdinc >> with -fself-tests. >> #undef

Re: [committed] libstdc++: Add deprecated attributes to old iostream members

On 19/08/20 12:29 +0100, Jonathan Wakely wrote: Back in 2017 I removed these prehistoric members (which were deprecated since C++98) for C++17 mode. But I didn't add deprecated attributes to most of them, so users didn't get any warning they would be going away. Apparently some poor souls do actu

Re: [Patch] Fortran: Add 'device_type' clause to OpenMP's declare target

Hi Andre, thanks for the comments. Am 18.08.20 um 19:33 schrieb Andre Vehreschild: > + case OMP_DEVICE_TYPE_HOST: > + MIO_NAME (ab_attribute) (AB_OMP_DEVICE_TYPE_NOHOST, attr_bits); > Why also NOHOST here? Copy and paste error. Well spotted. Thanks! (I wonder why it didn't show up in

Re: [PATCH v2] libgcc: Use `-fasynchronous-unwind-tables' for LIB2_DIVMOD_FUNCS

On Tue, 18 Aug 2020, Richard Earnshaw wrote: > > Complement commit b932f770f70d ("x86_64 frame unwind info"), SVN r46374, > > , and replace > > `-fexceptions -fnon-call-exceptions' with `-fasynchronous-unwind-tables' > > in LIB2_DIVMOD_F

PING [PATCH] x86: Add cmpmemsi for -minline-all-stringops

On Tue, May 19, 2020 at 5:14 AM H.J. Lu wrote: > > On Tue, May 19, 2020 at 1:48 AM Uros Bizjak wrote: > > > > On Sun, May 17, 2020 at 7:06 PM H.J. Lu wrote: > > > > > > Duplicate the cmpstrn pattern for cmpmem. The only difference is that > > > the length argument of cmpmem is guaranteed to be

PING [PATCH] x86: Inline strncmp only with -minline-all-stringops

On Wed, Jul 15, 2020 at 10:42:27AM -0700, H.J. Lu wrote: > Expand strncmp to "repz cmpsb" only with -minline-all-stringops since > "repz cmpsb" can be much slower than strncmp function implemented with > vector instructions, see > > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=43052 > > gcc/ > >

Re: [PATCH v2] libgcc: Use `-fasynchronous-unwind-tables' for LIB2_DIVMOD_FUNCS

On 19/08/2020 13:54, Maciej W. Rozycki via Gcc-patches wrote: > On Tue, 18 Aug 2020, Richard Earnshaw wrote: > >>> Complement commit b932f770f70d ("x86_64 frame unwind info"), SVN r46374, >>> , and replace >>> `-fexceptions -fnon-call-exc

Re: [committed] libstdc++: Add deprecated attributes to old iostream members

On 19/08/20 12:29 +0100, Jonathan Wakely wrote: Back in 2017 I removed these prehistoric members (which were deprecated since C++98) for C++17 mode. But I didn't add deprecated attributes to most of them, so users didn't get any warning they would be going away. Apparently some poor souls do actu

[PATCH] rs6000: Enable more sibcalls when TOC is not preserved

A function compiled with the PC-relative addressing model does not require r2 to contain a TOC pointer, and does not guarantee that r2 will be preserved for its caller. Such a function can make sibcalls without restriction based on TOC preservation rules. However, a caller that does preserve r2 c

Re: [PATCH] rs6000: Enable more sibcalls when TOC is not preserved

I failed to mention that this has been bootstrapped and tested on powerpc64le-unknown-linux-gnu, with no regressions.  Is this ok for trunk? Thanks, Bill On 8/19/20 9:40 AM, Bill Schmidt via Gcc-patches wrote: A function compiled with the PC-relative addressing model does not require r2 to con

[wwwdocs] Remove stray '>' character

Pushed to wwwdocs. commit e8120aa3ecc3dec9c6ddcd3add2326e94fe5fb1e Author: Jonathan Wakely Date: Wed Aug 19 15:41:44 2020 +0100 Remove stray '>' character diff --git a/htdocs/bugs/index.html b/htdocs/bugs/index.html index 66d9138f..a6631d8a 100644 --- a/htdocs/bugs/index.html +++ b/htdoc

[PING][PATCH] correct handling of indices into arrays with elements larger than 1 (PR c++/96511)

Ping: https://gcc.gnu.org/pipermail/gcc-patches/2020-August/551783.html On 8/11/20 10:19 AM, Martin Sebor wrote: -Wplacement-new handles array indices and pointer offsets the same: by adjusting them by the size of the element.  That's correct for the latter but wrong for the former, causing fals

[committed] i386: Use code_for_ instead of gen_ for parameterized names more.

Some builtins are better expanded to patterns with parametrized names via code_for_ than gen_ helpers. No functional changes. 2020-08-19 Uroš Bizjak gcc/ChangeLog: * config/i386/i386-expand.c (ix86_expand_builtin) [case IX86_BUILTIN_ENQCMD, case IX86_BUILTIN_ENQCMDS]: Rewrite exp

[committed] libstdc++: Make __int128 meet integer-class requirements [PR 96042]

Because __int128 can be used as the difference type for iota_view, we need to ensure that it meets the requirements of an integer-class type. The requirements in [iterator.concept.winc] p10 include numeric_limits being specialized and giving meaningful answers. Currently we only specialize numeric_

[PATCH v2][GCC] arm: Add +nomve and +nomve.fp options to -mcpu=cortex-m55

From: Joe Ramsay Hi all, This patch rearranges feature bits for MVE and FP to implement the following flags for -mcpu=cortex-m55. - +nomve:equivalent to armv8.1-m.main+fp.dp+dsp. - +nomve.fp: equivalent to armv8.1-m.main+mve+fp.dp (+dsp is implied by +mve). - +nofp: equivalent to

[committed] libstdc++: Remove deprecated comparison operators for RB trees

These functions were deprecated in GCC 9.1.0 because they are never used by the library. This patch removes them for GCC 11. libstdc++-v3/ChangeLog: * include/bits/stl_tree.h (operator!=, operator>, operator<=) (operator>=): Remove deprecated functions. Tested powerpc64le-linux.

Re: [PATCH] PR libstdc++/71579 assert that type traits are not misused with an incomplete type

ср, 19 авг. 2020 г. в 14:29, Jonathan Wakely : <...> > Do we also want to check > (std::__is_complete_or_unbounded(__type_identity<_ArgTypes>{}) && ...) > for invoke_result and the is_invocable traits? > > We can use a fold expression there, because those traits are not > defined before C++17. Goo

Re: [PATCH 1/2] Add new RTX instruction class FILLER_INSN

[ Please don't post new patch series as replies to old ] On Wed, Jul 22, 2020 at 12:02:33PM +0200, Andrea Corallo wrote: > This first patch implements the addition of a new RTX instruction class > FILLER_INSN, which has been white listed to allow placement of NOPs > outside of a basic block. This

Re: [PATCH 1/2] Add new RTX instruction class FILLER_INSN

On Wed, Aug 19, 2020 at 11:13:40AM +0200, Andrea Corallo wrote: > Segher Boessenkool writes: > > So I wonder if this cannot be done with some kind of NOTE, instead? > > I was having a look into reworking this using an insn note as (IIUC) > suggested. The idea is appealing but looking into insn-n

Re: [PATCH] bb-reorder: Remove a misfiring micro-optimization (PR96475)

On Wed, Aug 19, 2020 at 01:10:36PM +0100, Richard Sandiford wrote: > Segher Boessenkool writes: > > When the compgotos pass copies the tail of blocks ending in an indirect > > jump, there is a micro-optimization to not copy the last one, since the > > original block will then just be deleted. Thi

Re: [PATCH 1/2] Add new RTX instruction class FILLER_INSN

Segher Boessenkool writes: > [ Please don't post new patch series as replies to old ] > > On Wed, Jul 22, 2020 at 12:02:33PM +0200, Andrea Corallo wrote: >> This first patch implements the addition of a new RTX instruction class >> FILLER_INSN, which has been white listed to allow placement of NO

Re: [PATCH] rs6000: Enable more sibcalls when TOC is not preserved

Hi! On Wed, Aug 19, 2020 at 09:40:16AM -0500, Bill Schmidt wrote: > A function compiled with the PC-relative addressing model does not > require r2 to contain a TOC pointer, and does not guarantee that r2 > will be preserved for its caller. Such a function can make sibcalls > without restriction

Re: [PATCH] bb-reorder: Remove a misfiring micro-optimization (PR96475)

Segher Boessenkool writes: > On Wed, Aug 19, 2020 at 01:10:36PM +0100, Richard Sandiford wrote: >> Segher Boessenkool writes: >> > When the compgotos pass copies the tail of blocks ending in an indirect >> > jump, there is a micro-optimization to not copy the last one, since the >> > original blo

[PATCH] rs6000: Fix extraneous characters in the documentation

Replace them with a whitespace in order to avoid artifacts in the HTML document. 2020-08-19 Tulio Magno Quites Machado Filho gcc/ * doc/extend.texi (PowerPC Built-in Functions): Replace extraneous characters with whitespace. --- gcc/doc/extend.texi | 6 +++--- 1 file changed,

Re: [EXTERNAL] Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

On 8/14/20 7:42 PM, Segher Boessenkool wrote: > I think your current code is fine; I hadn't considered Bill's upcoming > rewrite. It is more important to make that go smoother than to fix some > aesthetics right now. > > Please check if the names for the builtins match the (future) > documentatio

[committed] analyzer: fix ICE on deref_rvalue on SK_COMPOUND [PR96643]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to master as r11-2772-g23ebfda0e352fa0a92c6b012458ecb65505a135f. gcc/analyzer/ChangeLog: PR analyzer/96643 * region-model.cc (region_model::deref_rvalue): Rather than attempting to handle all svalue kinds

[committed] analyzer: fix ICE on folding vector 0 [PR96705]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to master as r11-2771-gfc02b568e2cd3f6a28d4b7c1063bbf8842c89aad. gcc/analyzer/ChangeLog: * region-model-manager.cc PR analyzer/96705 (region_model_manager::maybe_fold_binop): Check that we have an

[committed] analyzer: fix ICE converting float to int [PR96699]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to master as r11-2770-g366bd1ac01a5249a463e64234674ad2d174faa9a. gcc/analyzer/ChangeLog: PR analyzer/96699 * region-model-manager.cc (region_model_manager::get_or_create_cast): Use FIX_TRUNC_EXPR for

Re: [committed] libstdc++: Make __int128 meet integer-class requirements [PR 96042]

On 19/08/20 17:00 +0100, Jonathan Wakely wrote: Because __int128 can be used as the difference type for iota_view, we need to ensure that it meets the requirements of an integer-class type. The requirements in [iterator.concept.winc] p10 include numeric_limits being specialized and giving meaning

[committed] [OG10] Re: Re: [Patch] [OpenMP, Fortran] Add structure/derived-type element mapping

If I got my tracking right, the og10 commit 4677091db1aa9d2a52e4839812bd73f47cc5e421 "[OpenMP, Fortran] Add structure/derived-type element mapping" regresses: [-PASS:-]{+FAIL:+} gfortran.dg/goacc/pr70828.f90 -O scan-tree-dump-times gimple "omp target oacc_data map\\(tofrom:MEM\\[\\(c_cha

Re: PING [Patch][Middle-end]Add -fzero-call-used-regs=[skip|used-gpr|all-gpr|used|all]

Hi, Based on all the previous discussion and more extensive study on ROP and its mitigation techniques these days, I came up with the following High-level proposal as requested, please take a look and let me know what I should change in this high-level design: > On Aug 6, 2020, at 6:37 PM, Segh

Re: [EXTERNAL] Re: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote: > On 8/14/20 7:42 PM, Segher Boessenkool wrote: > > I think your current code is fine; I hadn't considered Bill's upcoming > > rewrite. It is more important to make that go smoother than to fix some > > aesthetics right now. > > > > P

[pushed] c++: Check satisfaction before non-dep convs. [CWG2369]

It's very hard to use concepts to protect a template from hard errors due to unwanted instantiation if constraints aren't checked until after doing all substitution and checking of non-dependent conversions. It was pretty straightforward to insert the satisfaction check into the logic, but I neede

Re: [PATCH 3/4] libstdc++: Add floating-point std::to_chars implementation

On Wed, 22 Jul 2020, Patrick Palka wrote: > On Mon, 20 Jul 2020, Patrick Palka wrote: > > > On Mon, 20 Jul 2020, Jonathan Wakely wrote: > > > > > On 20/07/20 08:53 -0400, Patrick Palka via Libstdc++ wrote: > > > > On Mon, 20 Jul 2020, Jonathan Wakely wrote: > > > > > > > > > On 19/07/20 23:37 -

Re: [PATCH 2/5] C front end support to detect out-of-bounds accesses to array parameters

On 8/17/20 4:09 PM, Joseph Myers wrote: On Thu, 13 Aug 2020, Martin Sebor via Gcc-patches wrote: * Maybe cdk_pointer is followed by cdk_attrs before cdk_id. In this case the code won't return. I think I see the problem you're pointing out (I just don't see how to trigger it or test that it d

Re: PING [Patch][Middle-end]Add -fzero-call-used-regs=[skip|used-gpr|all-gpr|used|all]

Hi! On Wed, Aug 19, 2020 at 03:05:36PM -0500, Qing Zhao wrote: > So, cleaning the scratch registers that are used to pass parameters at return > instructions should > effectively mitigate ROP attack. But that is *very* expensive, in general. Instead of doing just a return instruction (which e

Re: [PATCH] bb-reorder: Remove a misfiring micro-optimization (PR96475)

Hi! On Wed, Aug 19, 2020 at 07:18:02PM +0100, Richard Sandiford wrote: > > I have never seen the second case misfiring in practice, only the first > > one! > > Shucks, I guessed the wrong way round :-) > > I'd argue that the first check isn't a micro-optimisation though. > It's testing whether t

Re: PING [Patch][Middle-end]Add -fzero-call-used-regs=[skip|used-gpr|all-gpr|used|all]

> On Aug 19, 2020, at 5:57 PM, Segher Boessenkool > wrote: > > Hi! > > On Wed, Aug 19, 2020 at 03:05:36PM -0500, Qing Zhao wrote: >> So, cleaning the scratch registers that are used to pass parameters at >> return instructions should >> effectively mitigate ROP attack. > > But that is *v

RE: [PATCH] rs6000, restrict bfloat convert intrinsic to Power 10. Fix BU_P10V macro definitions.

On Wed, 2020-08-19 at 15:16 -0500, Segher Boessenkool wrote: > On Wed, Aug 19, 2020 at 02:19:12PM -0500, Peter Bergner wrote: > > On 8/14/20 7:42 PM, Segher Boessenkool wrote: > > > I think your current code is fine; I hadn't considered Bill's > > > upcoming > > > rewrite. It is more important to

Re: [PATCH 2/5] C front end support to detect out-of-bounds accesses to array parameters

On Wed, 19 Aug 2020, Martin Sebor via Gcc-patches wrote: > > I think you need a while loop there, not just an if, to account for the > > case of multiple consecutive cdk_attrs. At least the GNU attribute syntax > > > > direct-declarator: > > [...] > > ( gnu-attributes[opt] declarator )

Re: [PATCH, rs6000] Add non-relative jump table support on Power Linux

Hi! Sorry this took so long to review. "I lost track of this patch", what can I say :-/ On Fri, Aug 14, 2020 at 03:31:05PM +0800, HAO CHEN GUI wrote: > This patch adds non-relative jump table support on Power Linux. It > implements ASM_OUTPUT_ADDR_VEC_ELT and adds four new expansions for > non

Re: [Patch 2/5] rs6000, 128-bit multiply, divide, modulo, shift, compare

On Thu, Aug 13, 2020 at 06:46:05PM -0500, will schmidt wrote: > > .../gcc.target/powerpc/int_128bit-runnable.c | 2254 + > > The path into the testsuite subdir looks strange there. Git abbreviated this. It is autogenerated (git diffstat), so there is nothing much you can do abou

[committed] analyzer: fix ICE on vector comparisons [PR96713]

Successfully bootstrapped & regrtested on x86_64-pc-linux-gnu. Pushed to master as r11-2776-g2f5951bd95e334d611f4be7bbe1a136c580f9c20. gcc/analyzer/ChangeLog: PR analyzer/96713 * region-model.cc (region_model::get_gassign_result): For comparisons, only use eval_condition wh

Re: [Patch 3/5] rs6000, Add TI to TD (128-bit DFP) and TD to TI support

Hi! On Tue, Aug 11, 2020 at 12:22:59PM -0700, Carl Love wrote: > +(define_insn "floattitd2" > + [(set (match_operand:TD 0 "gpc_reg_operand" "=d") > + (float:TD (match_operand:TI 1 "gpc_reg_operand" "v")))] > + "TARGET_TI_VECTOR_OPS" > + "dcffixqq %0,%1" > + [(set_attr "type" "dfp")]) I wo

[PATCH PR96698] aarch64: ICE during GIMPLE pass:vect

Hi, This is a simple fix for PR96698. For the test case, there are two PHIs in the inner loop in pass_vect [local count: 719407024]: # b_26 = PHI <0(4), b_15(10)> # c_27 = PHI <0(4), b_26(10)> c_27 = PHI <0(4), b_26(10)>

[PATCH] Check calls before loop unrolling

Hi, When unroll loops, if there are calls inside the loop, those calls may raise negative impacts for unrolling. This patch adds a param param_max_unrolled_calls, and checks if the number of calls inside the loop bigger than this param, loop is prevent from unrolling. This patch is checking the