Re: [PATCH 1/2] rs6000: Init V4SF vector without converting SP to DP

Hi! On Thu, Jul 09, 2020 at 09:14:44PM -0500, Xiong Hu Luo wrote: > Move V4SF to V4SI, init vector like V4SI and move to V4SF back. > Better instruction sequence could be generated on Power9: > The point is to use lwz to avoid converting the single-precision to > double-precision upon load, pack

Re: [PATCH 2/2] rs6000: Define define_insn_and_split to split unspec sldi+or to rldimi

Hi! On Thu, Jul 09, 2020 at 09:14:45PM -0500, Xiong Hu Luo wrote: > * config/rs6000/rs6000.md (rotl_unspec): New > define_insn_and_split. > +; rldimi with UNSPEC_SI_FROM_SF. > +(define_insn_and_split "*rotl_unspec" Please have rotldi3_insert in the name. "unspec" in the name doesn't

Re: [PATCH] rs6000: Define movsf_from_si2 to extract high part SF element from DImode[PR89310]

Hi! On Fri, Jul 10, 2020 at 09:39:40AM +0800, luoxhu wrote: > OK, seems the md file needs a format tool too... Heh. Just make sure it looks good (that is, does what it looks like), looks like the rest, etc. It's hard to do anything nice with unspecs, [ ] lists do not format well. > >> + "TARG

Re: [PATCH] RISC-V: Fix regular expression in target-specific test

On Fri, Jul 10, 2020 at 6:53 AM Simon Cook wrote: > Some square brackets were missing escape characters, causing DejaGnu to > try and call a proc with the name "at". > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/read-thread-pointer.c: Fix escaping on > regular expression. Th

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