Hi:
+/* Optimize vector MUL generation for V8QI, V16QI and V32QI
+ under TARGET_AVX512BW. i.e. for v16qi a * b, it has
+
+ vpmovzxbw ymm2, xmm0
+ vpmovzxbw ymm3, xmm1
+ vpmullw ymm4, ymm2, ymm3
+ vpmovwb xmm0, ymm4
+
+ it would take less instructions than ix86_expand_vecop_qihi.
+
On June 4, 2020 10:22:55 PM GMT+02:00, Alexandre Oliva
wrote:
>On Jun 3, 2020, Martin Liška wrote:
>
>> On 6/3/20 5:58 AM, Alexandre Oliva wrote:
>>> Please let me know if you'd prefer me to take this PR over.
>
>> Yes, please take a look.
>
>Here's what I've regstrapped on x86_64-linux-gnu. I
Hi!
In January I've added patterns to optimize SImode -> DImode sign or zero
extension of __builtin_popcount, this patch does the same for
__builtin_c[lt]z. Like most other instructions, the [tl]zcntl instructions
clear the upper 32 bits of the destination register and as the instructions
only re
On Fri, Jun 5, 2020 at 8:45 AM Jakub Jelinek wrote:
>
> Hi!
>
> In January I've added patterns to optimize SImode -> DImode sign or zero
> extension of __builtin_popcount, this patch does the same for
> __builtin_c[lt]z. Like most other instructions, the [tl]zcntl instructions
> clear the upper 3
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