Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_eq3): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
(mmx_gt3): Likewise.
---
Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_andnot3): Also allow
TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 del
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_v8qi3): Likewise.
(smaxmin:v4hi3): New.
(umaxmin:v8qi3
Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/m
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
SSE support.
---
gcc/c
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_mulv4hi3): Also allow
TARGET_MMX_WITH_SSE.
(mulv4hi3): New.
(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
---
Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_uavgv4hi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 26 +
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(mmx_pshufw_1): Add SSE emulation.
(*vec_dupv4hi): Changed to define_insn_and_split a
Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
PR target/89021
* config/i386/sse.md (sse_cvtps2pi): Add SSE emulation.
(sse_cvttps2pi): Likewise.
---
gcc/config/i386/sse.md | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
TARGET_MMX and TARGET_MMX_WITH_SSE.
(*mmx_umulv4hi3_highpart): Add SSE emulation.
---
gcc/config/i38
Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_pinsrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 33 ++
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
destination XMM register. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (sse_cvtpi2ps): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
---
gcc/config/i3
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_palignrdi): Changed to
define_insn_an
Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign3): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i3
Emulate MMX ssse3_phdv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phdv2si3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
There is no V4HI pmulhrsw in AVX512BW and V4HI/V8HI pmulhrsw don't require
AVX2. To support TARGET_MMX_WITH_SSE, replace nonimmediate_operand with
register_pmulhrswmem_operand in _pmulhrsw3.
PR target/89372
* config/i386/predicates.md (register_pmulhrswmem_operand): New.
*
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/con
PR target/89021
* config/i386/mmx.md (MMXMODE:mov): Also allow
TARGET_MMX_WITH_SSE.
(MMXMODE:*mov_internal): Likewise.
(MMXMODE:movmisalign): Likewise.
---
gcc/config/i386/mmx.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/c
Emulate MMX abs2 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/sse.md (abs2): Add SSE emulation.
---
gcc/config/i386/sse.md | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/conf
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/
Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation.
---
gcc/config/i386/sse.md | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --gi
Emulate MMX movntq with SSE2 movntidi. Only register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (sse_movntq): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/gcc/config/i386/mmx
This pach enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with
SSE2.
---
gcc/config/i386/i386.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/xmmintrin.h: Em
PR target/89021
* config/i386/i386.c (ix86_expand_vector_init_duplicate): Set
mmx_ok to true if TARGET_MMX_WITH_SSE is true.
(ix86_expand_vector_init_one_nonzero): Likewise.
(ix86_expand_vector_init_one_var): Likewise.
(ix86_expand_vector_init_general
From: Uros Bizjak
2019-02-14 Uroš Bizjak
PR target/89021
* config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
* config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto.
(*vec_concatv2sf_sse): Ditto.
(*vec_concatv2si_sse4_1): Ditto.
(*vec
With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
when MMX is disabled.
PR target/89021
* config/i386/mmx.md (mmx_): Renamed to ...
(mmx__1): This.
(mmx_): New expander.
---
gcc/config/i386/mmx.md | 29 -
1 file ch
Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow
broadcast from integer register for AVX512BW with TARGET_AVX512VL.
Only SSE register source operand is allowed.
PR target/89021
* config/i386/constraints.md (Yw): New constraint.
* config/i386/mmx.md (*vec_
Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phwv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(*mmx_uavgv8qi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 25 +
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
support.
(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 26 -
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.
For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.
gcc/
PR target/89021
* config/i386/i386-builtin.
On Fri, Feb 15, 2019 at 9:50 AM Uros Bizjak wrote:
>
> On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote:
> >
> > On x86-64, since __m64 is returned and passed in XMM registers, we can
> > emulate MMX intrinsics with SSE instructions. To support it, we added
> >
> > #define TARGET_MMX_WITH_SSE (TARG
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pshufbv8qi3): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. A
On 2/6/19 9:16 AM, Martin Sebor wrote:
The manual documents the -Wno-missing-attributes form of the option
as if it was enabled by default, even though it's enabled by -Wall
(I can't get this -Wno- convention straight in my head). I also
got private comments on the documentation of the option su
On 2/6/19 11:15 AM, Martin Sebor wrote:
[snip]
But whatever. Attached is a change with the subsentences reversed.
This version of the patch is OK.
-Sandra
On 2/13/19 2:46 PM, Martin Sebor wrote:
The attached patch adds documentation for the __has_attribute (and
__has_cpp_attribute) and __has_include operators added in r215752.
Thanks!
I was a little unsure where to add this, whether the preprocessor
manual or the GCC manual, or both. It seems
On 2/13/19 4:33 PM, Martin Sebor wrote:
Index: gcc/doc/extend.texi
===
--- gcc/doc/extend.texi (revision 268856)
+++ gcc/doc/extend.texi (working copy)
@@ -12890,6 +12890,22 @@ built-in in this case, because it has no opportuni
opt
On 2/11/19 6:03 PM, Marek Polacek wrote:
On Mon, Feb 11, 2019 at 01:43:36PM -0500, Jason Merrill wrote:
On 2/7/19 6:02 PM, Marek Polacek wrote:
Since r268321 we can call digest_init even in a template, when the compound
literal isn't instantiation-dependent.
Right. And since digest_init modi
On 2/14/19 4:20 PM, David Malcolm wrote:
On Thu, 2019-02-14 at 17:32 +0100, Jakub Jelinek wrote:
On Thu, Feb 14, 2019 at 11:26:15AM -0500, David Malcolm wrote:
There's an asymmetry in the warning; it's looking for a comparison
of a
LHS expression against an RHS constant 0, spelled as "0".
If w
On 2/14/19 7:09 PM, will wray wrote:
Thanks Jason.
Adding this 'else if' condition afterwards seems to work:
else if (BRACE_ENCLOSED_INITIALIZER_P (CONSTRUCTOR_ELT
(stripped_init,0)->value))
{
if (complain & tf_error)
error ("too many braces around scalar i
Hi!
Both the C and C++ standard guarantee that the argc argument to main is
non-negative, the following patch sets (or adjusts) the corresponding
SSA_NAME_RANGE_INFO. While main is just one, with IPA VRP it can also
propagate etc. I had to change one testcase because it started optimizing
it bet
Hi!
On the following testcase, we've regressed in bar since 8.x, in 8.x
store merging came up with mem = 64-bit constant, but starting with the
change to transform {0,1,2,3,4,5,6,7} char initializers into STRING_CSTs,
we don't do that anymore. The mem = STRING_CST expansion can do that,
but only
Hi!
This is something I've noticed in a s390 change I'll post soon (where it was
even completely unnecessary), but it applies to i386 backend too.
Seems we have lots of .bss global state, 66x 64-byte and 61x 128-byte long
static buffers. Instead of doing
static char buf[128];
...
s{,n}print
On Fri, Feb 15, 2019 at 08:59:29PM +0100, Matthias Klose wrote:
> On 15.02.19 15:52, Ian Lance Taylor wrote:
> > This patch by Robin Dapp adds S/390 support to the internal/cpu
> > package. This partially addresses PR 89123. I bootstrapped it on
> > x86_64-pc-linux-gnu, which means little. Commi
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