Re: [PATCH] Fix X +- C1 CMP C2 match.pd folding with -fwrapv (PR tree-optimization/80788)

On November 27, 2017 11:36:23 PM GMT+01:00, Jakub Jelinek wrote: >Hi! > >This transformation turns it into a false or true if TREE_OVERFLOW >and TYPE_OVERFLOW_UNDEFINED, but if TREE_OVERFLOW is set, but not >TYPE_OVERFLOW_UNDEFINED, we leak the overflow bit into the IL, which >then >confuses the

Re: [Ping][PATCH v3] Fix Incorrect ASan global variables alignment on arm (PR sanitizer/81697)

(CC'ing Jakub and Ramana) Hi, I would like to ping the following patch: https://gcc.gnu.org/ml/gcc-patches/2017-10/msg02288.html Fix Incorrect ASan global variables alignment on arm (PR sanitizer/81697) -Maxim gcc/ChangeLog: 2017-11-28 Maxim Ostapenko PR sanitizer/81697 * asan.c (asan_pr

Re: [104/nnn] poly_int: GET_MODE_PRECISION

On 10/23/2017 11:42 AM, Richard Sandiford wrote: > This patch changes GET_MODE_PRECISION from an unsigned short > to a poly_uint16. > > > 2017-10-23 Richard Sandiford > Alan Hayward > David Sherwood > > gcc/ > * machmode.h (mode_precision): Change from unsigned s

Re: [098/nnn] poly_int: load_register_parameters

On 10/23/2017 11:40 AM, Richard Sandiford wrote: > This patch makes load_register_parameters cope with polynomial sizes. > The requirement here is that any register parameters with non-constant > sizes must either have a specific mode (e.g. a variable-length vector > mode) or must be represented wi

<    1   2