Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the French team of translators. The file is available at:
http://translationproject.org/latest/gcc/fr.po
(This file, 'gcc-7.2.0.fr.po', has just
On Tue, Aug 15, 2017 at 6:33 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Tue, Aug 15, 2017 at 11:28 AM, Bin Cheng wrote:
>>> Hi,
>>> This patch fixes PR81832. Root cause for the ICE is:
>>> 1) Loop has distributed inner loop.
>>> 2) The guarding function call IFN_LOOP_DIST_C
"Bin.Cheng" writes:
> On Tue, Aug 15, 2017 at 6:33 PM, Richard Sandiford
> wrote:
>> Richard Biener writes:
>>> On Tue, Aug 15, 2017 at 11:28 AM, Bin Cheng wrote:
Hi,
This patch fixes PR81832. Root cause for the ICE is:
1) Loop has distributed inner loop.
2) The guardin
On Wed, Aug 16, 2017 at 10:31 AM, Richard Sandiford
wrote:
> "Bin.Cheng" writes:
>> On Tue, Aug 15, 2017 at 6:33 PM, Richard Sandiford
>> wrote:
>>> Richard Biener writes:
On Tue, Aug 15, 2017 at 11:28 AM, Bin Cheng wrote:
> Hi,
> This patch fixes PR81832. Root cause for the ICE
On Mon, Aug 14, 2017 at 10:22:09AM +0200, Richard Biener wrote:
> On Tue, Aug 8, 2017 at 7:23 PM, Marek Polacek wrote:
> > On Mon, Aug 07, 2017 at 04:07:49PM +0200, Richard Biener wrote:
> >> On August 7, 2017 11:09:59 AM GMT+02:00, Marek Polacek
> >> wrote:
> >> >On Mon, Aug 07, 2017 at 10:58:0
On Tue, Aug 15, 2017 at 9:21 PM, Uros Bizjak wrote:
> On Tue, Aug 15, 2017 at 4:59 PM, Richard Biener
> wrote:
>
>> So I'd try the "easy" way of expanding if (__builtin_cpu_supports ("sse4.1"))
>> as the sse4.1 sequence is just a single instruction. The interesting part
>> of the story will be t
On Wed, Aug 16, 2017 at 11:22 AM, Bin.Cheng wrote:
> On Tue, Aug 15, 2017 at 6:33 PM, Richard Sandiford
> wrote:
>> Richard Biener writes:
>>> On Tue, Aug 15, 2017 at 11:28 AM, Bin Cheng wrote:
Hi,
This patch fixes PR81832. Root cause for the ICE is:
1) Loop has distributed in
On Wed, Aug 16, 2017 at 12:43 PM, Richard Biener
wrote:
> On Tue, Aug 15, 2017 at 9:21 PM, Uros Bizjak wrote:
>> On Tue, Aug 15, 2017 at 4:59 PM, Richard Biener
>> wrote:
>>
>>> So I'd try the "easy" way of expanding if (__builtin_cpu_supports
>>> ("sse4.1"))
>>> as the sse4.1 sequence is just
On Wed, Aug 16, 2017 at 12:48 PM, Uros Bizjak wrote:
> On Wed, Aug 16, 2017 at 12:43 PM, Richard Biener
> wrote:
>> On Tue, Aug 15, 2017 at 9:21 PM, Uros Bizjak wrote:
>>> On Tue, Aug 15, 2017 at 4:59 PM, Richard Biener
>>> wrote:
>>>
So I'd try the "easy" way of expanding if (__builtin_cp
On Wed, Aug 16, 2017 at 12:33 PM, Marek Polacek wrote:
> On Mon, Aug 14, 2017 at 10:22:09AM +0200, Richard Biener wrote:
>> On Tue, Aug 8, 2017 at 7:23 PM, Marek Polacek wrote:
>> > On Mon, Aug 07, 2017 at 04:07:49PM +0200, Richard Biener wrote:
>> >> On August 7, 2017 11:09:59 AM GMT+02:00, Mare
On Wed, Aug 16, 2017 at 12:51 PM, Uros Bizjak wrote:
> On Wed, Aug 16, 2017 at 12:48 PM, Uros Bizjak wrote:
>> On Wed, Aug 16, 2017 at 12:43 PM, Richard Biener
>> wrote:
>>> On Tue, Aug 15, 2017 at 9:21 PM, Uros Bizjak wrote:
On Tue, Aug 15, 2017 at 4:59 PM, Richard Biener
wrote:
>>>
On Wed, Aug 16, 2017 at 12:55 PM, Richard Biener
wrote:
> On Wed, Aug 16, 2017 at 12:51 PM, Uros Bizjak wrote:
>> On Wed, Aug 16, 2017 at 12:48 PM, Uros Bizjak wrote:
>>> On Wed, Aug 16, 2017 at 12:43 PM, Richard Biener
>>> wrote:
On Tue, Aug 15, 2017 at 9:21 PM, Uros Bizjak wrote:
>
On 28.07.2017 09:34, Richard Biener wrote:
On Thu, Jul 27, 2017 at 3:32 PM, Georg-Johann Lay wrote:
On 27.07.2017 14:34, Richard Biener wrote:
On Thu, Jul 27, 2017 at 2:29 PM, Georg-Johann Lay wrote:
For some targets, the best place to put read-only lookup tables as
generated by -ftree-swi
The first loop in the testcase regressed after my recent changes to
dr_analyze_innermost. Previously we would treat "i" as an iv even
for bb analysis and end up with:
DR_BASE_ADDRESS: p or q
DR_OFFSET: 0
DR_INIT: 0 or 4
DR_STEP: 16
We now always keep the step as 0 instead, so for an
Richard Sandiford writes:
> The first loop in the testcase regressed after my recent changes to
> dr_analyze_innermost. Previously we would treat "i" as an iv even
> for bb analysis and end up with:
>
>DR_BASE_ADDRESS: p or q
>DR_OFFSET: 0
>DR_INIT: 0 or 4
>DR_STEP: 16
>
> We now
On Wed, Aug 16, 2017 at 2:38 PM, Richard Sandiford
wrote:
> The first loop in the testcase regressed after my recent changes to
> dr_analyze_innermost. Previously we would treat "i" as an iv even
> for bb analysis and end up with:
>
>DR_BASE_ADDRESS: p or q
>DR_OFFSET: 0
>DR_INIT: 0 o
This patch improves -Wtautological-compare so that it also detects
bitwise comparisons involving & and | that are always true or false, e.g.
if ((a & 16) == 10)
return 1;
can never be true. Note that e.g. "(a & 9) == 8" is *not* always false
or true.
I think it's pretty straightforward wi
On Tue, 2017-08-15 at 23:44 +, Joseph Myers wrote:
>
> > This is an older issue. Please also add a reference to PR 67712 in
> > your commit. Can you also apply it to GCC 6 branch please?
> I can't reproduce the problem with GCC 6 branch; the glibc testsuite
> builds fine without out-of-mem
On Wed, 2017-08-16 at 16:29 +0200, Marek Polacek wrote:
> This patch improves -Wtautological-compare so that it also detects
> bitwise comparisons involving & and | that are always true or false,
> e.g.
>
> if ((a & 16) == 10)
> return 1;
>
> can never be true. Note that e.g. "(a & 9) == 8
Hi Richard,
I have changed the condition as you suggest below. OK for trunk?
Jackson.
On 08/11/2017 02:56 PM, Richard Earnshaw (lists) wrote:
On 10/08/17 14:12, Jackson Woodruff wrote:
Hi all,
This patch changes patterns in aarch64-simd.md to replace
moviv0.4s, 0
strq0, [
On 8/16/17, David Malcolm wrote:
> On Wed, 2017-08-16 at 16:29 +0200, Marek Polacek wrote:
>> This patch improves -Wtautological-compare so that it also detects
>> bitwise comparisons involving & and | that are always true or false,
>> e.g.
>>
>> if ((a & 16) == 10)
>> return 1;
>>
>> can ne
On Wed, Aug 16, 2017 at 11:07:36AM -0400, David Malcolm wrote:
> On Wed, 2017-08-16 at 16:29 +0200, Marek Polacek wrote:
> > This patch improves -Wtautological-compare so that it also detects
> > bitwise comparisons involving & and | that are always true or false,
> > e.g.
> >
> > if ((a & 16) =
Hello!
Attached patch allows memory operands for btr/bts and btc
instructions. The previous comment was wrong, these instructions do
not enforce atomic operations with memory operand without "lock"
prefix. Instructions in its RMW form with immediate operand are not
slower than corresponding logic
"Bin.Cheng" writes:
> On Wed, Aug 16, 2017 at 2:38 PM, Richard Sandiford
> wrote:
>> The first loop in the testcase regressed after my recent changes to
>> dr_analyze_innermost. Previously we would treat "i" as an iv even
>> for bb analysis and end up with:
>>
>>DR_BASE_ADDRESS: p or q
>>
On Wed, Aug 16, 2017 at 5:00 PM, Richard Sandiford
wrote:
> "Bin.Cheng" writes:
>> On Wed, Aug 16, 2017 at 2:38 PM, Richard Sandiford
>> wrote:
>>> The first loop in the testcase regressed after my recent changes to
>>> dr_analyze_innermost. Previously we would treat "i" as an iv even
>>> for b
Bug 81859 points out that my fix for bug 81586 wasn't quite
right (or complete): the argument of a %.*s directive need
not be a nul-terminated string when the precision is less
than the initialized size of the array the argument points
to. The attached tweak uses strnlen to avoid reading past
th
On 07/13/2017 02:51 AM, Richard Sandiford wrote:
> This patch changes the iv modes in rtx_iv from machine_mode
> to scalar_int_mode. It also passes the mode of the iv down
> to subroutines; this avoids the previous situation in which
> the mode information was sometimes lost and had to be added
>
On 07/13/2017 02:52 AM, Richard Sandiford wrote:
> get_best_mode always returns a scalar_int_mode on success,
> so this patch makes that explicit in the type system. Also,
> the "largest_mode" argument is used simply to provide a maximum
> size, and in practice that size is always a compile-time c
On 07/13/2017 02:52 AM, Richard Sandiford wrote:
> insv, extv and eztzv modify or read a field in a register or
> memory. The field always has a scalar integer mode, while the
> register or memory either has a scalar integer mode or BLKmode.
> The mode of the bit position is also a scalar integer.
On 07/13/2017 02:53 AM, Richard Sandiford wrote:
> force_to_mode exits partway through for modes that aren't scalar
> integers. This patch splits the remainder of the function out
> into a subroutine, force_int_to_mode, so that the modes from that
> point on can have type scalar_int_mode.
>
> The
On 07/13/2017 02:53 AM, Richard Sandiford wrote:
> This patch makes simplify_shift_const_1 use scalar_int_modes
> for all code that is specific to scalars rather than vectors.
> This includes situations in which the new shift mode is different
> from the original one, since the function never chang
"Bin.Cheng" writes:
> On Wed, Aug 16, 2017 at 5:00 PM, Richard Sandiford
> wrote:
>> "Bin.Cheng" writes:
>>> On Wed, Aug 16, 2017 at 2:38 PM, Richard Sandiford
>>> wrote:
The first loop in the testcase regressed after my recent changes to
dr_analyze_innermost. Previously we would tre
This, almost obvious, patch merges the older SIGPIPE conditional into
the new switch I added. I found the FALLTHROUGH marker needed to be
outside the #if, which was a little annoying.
I changed the backtrace error message to also explicitly say it was a
signal wot did it.
ok?
nathan
--
Nat
On Wed, Aug 16, 2017 at 02:24:10PM -0400, Nathan Sidwell wrote:
> This, almost obvious, patch merges the older SIGPIPE conditional into the
> new switch I added. I found the FALLTHROUGH marker needed to be outside the
> #if, which was a little annoying.
True, it needs to precede the casea token.
2017-08-16 Uros Bizjak
* c-c++-common/patchable_function_entry-decl.c (dg-final): Adapt
scan-assembler-times for alpha*-*-*.
* c-c++-common/patchable_function_entry-default.c (dg-final): Ditto.
* c-c++-common/patchable_function_entry-definition.c (dg-final): Ditto.
Tested on al
This patch by Tony Reix fixes dumpregs on i386 to use the right type,
implements dumpregs for PPC Linux/AIX, and retrieves the PC value on
AIX. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu.
Committed to mainline.
Ian
Index: gcc/go/gofrontend/MERGE
=
Successfully bootstrapped®rtested on x86_64-pc-linux-gnu.
Committed to trunk as r251128.
gcc/ChangeLog:
* diagnostic-show-locus.c (colorizer::m_caret): Remove unused
field.
---
gcc/diagnostic-show-locus.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/diagnostic-show-locu
These is the third major contribution of X86 intrinsic equivalent
headers for PPC64LE.
X86 SSE technology was the second SIMD extension which added wider
128-bit vector (XMM) registers and single precision float capability.
They also addressed missing MMX capabilies and provided transfers (move,
p
My excision of TYPE_METHODS frees up the TYPE_MAX_VALUES_RAW slot in
RECORD_TYPEs. This patch moves TYPE_BINFO to there.
That move frees up type_non_common::binfo, which I rename to
type_non_common::lang_1 and adjust TYPE_LANG_SLOT_1 to allow any type
slot to use it.
TYPE_LANG_SLOT_1 is use
This it part 2/3 for contributing PPC64LE support for X86 SSE
instrisics. This patch includes the new (for PPC) xmmintrin.h and
associated config.gcc changes.
This submission implements all the SSE Technology intrinsic functions
except those associated with directly accessing and updating the MX
S
This it part 3/3 for contributing PPC64LE support for X86 SSE
instrisics. This patch includes testsuite/gcc.target tests for the
intrinsics included by xmmintrin.h.
For these tests I added -Wno-psabi to dg-options to suppress warnings
associated with the vector ABI change in GCC5. These warning a
On Wed, 2017-08-16 at 10:12 -0600, Martin Sebor wrote:
> PR c/81859 - [8 Regression] valgrind error from
> warn_about_normalization
>
> gcc/ChangeLog:
>
> PR c/81859
> * pretty-print.c (pp_format): Use strnlen in %.*s to avoid
> reading
> past the end of an array.
> (test_
This patch by Tony Reix improves the AIX netpoll code used by libgo.
Bootstrapped on x86_64-pc-linux-gnu. Committed to mainline.
Ian
Index: gcc/go/gofrontend/MERGE
===
--- gcc/go/gofrontend/MERGE (revision 251127)
+++ gcc/go/gofr
Hi Mike,
On Mon, Aug 14, 2017 at 03:21:42PM -0400, Michael Meissner wrote:
> This patch enables the _Float128 keyword for the C langauge all of the time
> for
> PowerPC VSX systems. The __float128 keyword continues to be only enabled if
> you use the -mfloat128 option.
Looks good, please commit
On Mon, Aug 14, 2017 at 04:28:25PM -0500, Peter Bergner wrote:
> The following patch fixes a performance issue when loading/storing/moving
> TImode values when using -mvsx-timode -mcpu=power7 with LRA. The problem is
> that the vsx_le_permute_ and vsx_le_perm_{load,store}_ patterns
> do no support
Jon,
Attached is the libstdc++ only patch to remove the pointless
const attribute from __pool::_M_destroy_thread_key(void*).
https://gcc.gnu.org/ml/gcc/2017-08/msg00027.html
I only belatedly now broke it out of the larger patch under
review here:
https://gcc.gnu.org/ml/gcc-patches/2017-08/
On Mon, Aug 14, 2017 at 06:02:51PM -0500, Peter Bergner wrote:
> The undocumented option -mvsx-timode was added because there were reload
> bugs we couldn't fix when we tried allowing TImode values in VSX registers.
> We used the option to allow TImode values in VSX registers when LRA was
> being u
On 8/16/17 5:30 PM, Segher Boessenkool wrote:
> On Mon, Aug 14, 2017 at 04:28:25PM -0500, Peter Bergner wrote:
>> + mr %0,%L1; mr %L0,%1
>
>mr %0,%L1\;mr %L0,%1
So you want the ';' escaped and the space removed? Ok.
>> + [(set (match_operand:VSX_TI 0 "int_reg_operand" "")
>
> You can
Hi!
On Tue, Aug 15, 2017 at 04:14:21PM -0500, Bill Schmidt wrote:
> One of Carl Love's proposed built-in function patches exposed a bug in the
> Power
> code that recognizes specific permute control vector patterns for a permute,
> and
> changes the permute to a more specific and more efficient
This patch enables -mfloat128 to be the default on PowerPC Linux VSX systems.
This patch depends on the libquadmatch/81848 patch being approved and
installed:
https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00977.html
In this patch, I removed the old undocumented -mfloat128-type switch, and made
th
Hi!
On Wed, Aug 16, 2017 at 08:05:04AM +0930, Alan Modra wrote:
> Repost with requested changes. I've extracted the logic that omits
> frame saves from rs6000_frame_related to a new function, because it's
> easier to document that way. The logic has been simplified a little
> too: fixed_reg_p do
Hi!
On Wed, Aug 16, 2017 at 02:11:31PM -0500, Steven Munroe wrote:
> These is the third major contribution of X86 intrinsic equivalent
> headers for PPC64LE.
> This patch just adds the mm_malloc.h header with is will be needed by
> xmmintrin.h and cleans up some noisy warnings from the previous M
On Wed, Aug 16, 2017 at 05:56:09PM -0500, Peter Bergner wrote:
> On 8/16/17 5:30 PM, Segher Boessenkool wrote:
> > On Mon, Aug 14, 2017 at 04:28:25PM -0500, Peter Bergner wrote:
> >> + mr %0,%L1; mr %L0,%1
> >
> >mr %0,%L1\;mr %L0,%1
>
> So you want the ';' escaped and the space removed? O
On Wed, Aug 16, 2017 at 06:23:13PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Wed, Aug 16, 2017 at 08:05:04AM +0930, Alan Modra wrote:
> > Repost with requested changes. I've extracted the logic that omits
> > frame saves from rs6000_frame_related to a new function, because it's
> > easier to
On Thu, Aug 17, 2017 at 11:25:27AM +0930, Alan Modra wrote:
> On Wed, Aug 16, 2017 at 06:23:13PM -0500, Segher Boessenkool wrote:
> > Maybe whatever is creating those instructions should set RTX_FRAME_RELATED_P
> > by itself? Not sure if that is nicer.
> >
> > Both this CR2 and R0 handling are pr
To make review easier I broke out the C++ changes for the attributes
work into a patch of their own. I also found the API I had asked
about, to look up a declaration based on one that's about to be
added/merged.
This patch depends on the foundation bits posted here:
https://gcc.gnu.org/ml/gcc
#01 of #08:
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01971.html
#02 of #08:
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01972.html
#03 of #08:
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01974.html
Need to reach some kind of closure on these, then I can start pinging
the target maintai
Hi!
On Wed, Aug 16, 2017 at 03:35:40PM -0500, Steven Munroe wrote:
> +extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__,
> __artificial__))
> +_mm_add_ss (__m128 __A, __m128 __B)
> +{
> +#ifdef _ARCH_PWR7
> + __m128 a, b, c;
> + static const __vector unsigned int mask = {0
On Wed, Aug 16, 2017 at 03:50:55PM -0500, Steven Munroe wrote:
> This it part 3/3 for contributing PPC64LE support for X86 SSE
> instrisics. This patch includes testsuite/gcc.target tests for the
> intrinsics included by xmmintrin.h.
> +#define CHECK_EXP(UINON_TYPE, VALUE_TYPE, FMT)
Ping. Original patch:
https://gcc.gnu.org/ml/gcc-patches/2017-08/msg00544.html
60 matches
Mail list logo
