On Wed, Jul 26, 2017 at 10:26 PM, Ian Lance Taylor wrote:
> On Sat, Jul 22, 2017 at 11:08 AM, Uros Bizjak wrote:
>>> This patch to the gotools Makefile adds tests to `make check`. We now
>>> test the runtime package using the newly built go tool, and test that
>>> cgo works by running the misc/c
On Tue, Aug 8, 2017 at 7:23 PM, Marek Polacek wrote:
> On Mon, Aug 07, 2017 at 04:07:49PM +0200, Richard Biener wrote:
>> On August 7, 2017 11:09:59 AM GMT+02:00, Marek Polacek
>> wrote:
>> >On Mon, Aug 07, 2017 at 10:58:09AM +0200, Jakub Jelinek wrote:
>> >> On Mon, Aug 07, 2017 at 10:47:51AM +
On Tue, Aug 8, 2017 at 10:20 PM, Richard Kenner
wrote:
>> Correct. It is truncated for integer shift, but not simd shift
>> instructions. We generate a pattern in the split that only generates
>> the integer shift instructions.
>
> That's unfortunate, because it would be nice to do this in simplif
Hi,
this patch fixes the wrong-code PR81844, where an omp for loop is
incorrectly removed by the compiler.
Consider the test-case from the patch.
It contains a omp for condition 'i > 0x7fffULL', where i is
of type unsigned long long int.
In c_parser_omp_for_loop, we first hav
On Thu, Aug 10, 2017 at 9:50 AM, Martin Liška wrote:
> On 08/02/2017 01:51 PM, Richard Biener wrote:
>> On Wed, Aug 2, 2017 at 1:20 PM, Martin Liška wrote:
>>> Hello.
>>>
>>> After some discussions with Honza, I've decided to convert current code in
>>> stmt.c that
>>> is responsible for switch
On Thu, Aug 10, 2017 at 6:39 PM, Pekka Jääskeläinen wrote:
> Hi,
>
> The attached patch adds a new switch -fftz-math which makes certain
> optimizations
> assume that "flush to zero" behavior of denormal inputs and outputs is
> not an optimization
> hint, but required behavior for semantical corre
Ping.
On Fri, Jul 28, 2017 at 12:37 PM, Bin Cheng wrote:
> Hi,
> This simple patch fixes the ICE by adding LTGT in vec_cmp
> pattern.
> I also modified the original test case into a compilation one since
> -fno-wrapping-math
> should not be used in general.
> Bootstrap and test on AArch64, test
HI,
This patch adds copying interface for dependence_info. The methodology
is we don't copy such information by default, and this interface should
be called explicitly when it is safe and necessary to do so. Just like
this patch uses the interface in ivopts.
Bootstrap and test in series. Is it O
Hi,
Given tree node (thus struct dependence_info) is kept and shadow copied on RTL,
it is unsafe to pass non-dependent info to RTL in case of loop unrolling etc.
This patch adds an interface clearing all dependence_info with fixed access
length tag before entering RTL world. We could do it just be
Hi,
This simple patch adds code dumping struct dependence_info.
Bootstrap and test in series. Is it OK?
Thanks,
bin
2017-08-10 Bin Cheng
* tree-pretty-print.c (dump_generic_node): Dump fixed length
tag in MEM_REF. Dump dependence info in TARGET_MEM_REF.From 60c58afac71860bdef
Hi,
This is the main patch recording runtime alias check information in struct
dependence_info and passing it along to later optimizers. It models graph
of runtime alias checks with some approximation; then sets
to the original data references and records it in hash map; at last, it
sets info to
Hi,
This simple patch adds new interface returning adjacent vertices for a vertex
in graph.
Bootstrap and test in series. Is it OK?
Thanks,
bin
2017-08-10 Bin Cheng
* graphds.c (adjacent_vertices): New function.
* graphds.h (adjacent_vertices): New declaration.From d84e4dd5b8
Hi,
This simple patch adds new field in struct dependence_info. The new field
indicates if non-dependence information is only valid for fixed memory access
length of this reference. There is a concern that this costs an additional
byte for all tree nodes, but I do not know easy way out because we
https://gcc.gnu.org/r251085
Fixed mentioned avr build hiccup that occurs when used with
Binutils < 2.29.
Johann
PR target/81754
PR target/81268
* config/avr/avr.opt (mgas-isr-prologues): New Var
avr_gasisr_prologues.
* config/avr/avr.md (gasisr, *gasisr):
Make sure adrp is used for literal loads.
committed as obvious.
gcc/testsuite/ChangeLog:
2017-08-14 Szabolcs Nagy
* gcc.target/aarch64/dbl_mov_immediate_1.c: Add
-mno-pc-relative-literal-loads.
diff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/testsuit
Hi Richard,
The base idea of the patch is to optimize for the (common) situation
where FTZ/DAZ
is controlled by a CPU-wide flag and we then need to only avoid compile-time
optimizations that assume semantics where denorm handling is on to support
the ‘forced FTZ/DAZ semantics’.
> This suggests on
Hi,
This patch fixes ICE reported in PR81799. It simply uses is_gimple_val rather
than is_gimple_condexpr.
Bootstap and test on x86_64. Is it OK?
Thanks,
bin
2017-08-11 Bin Cheng
PR tree-optimization/81799
* tree-loop-distribution.c (version_loop_by_alias_check): Force
On Mon, Aug 14, 2017 at 12:45 PM, Pekka Jääskeläinen wrote:
> Hi Richard,
>
> The base idea of the patch is to optimize for the (common) situation
> where FTZ/DAZ
> is controlled by a CPU-wide flag and we then need to only avoid compile-time
> optimizations that assume semantics where denorm handl
On Wed, Aug 9, 2017 at 1:39 PM, Martin Liška wrote:
> On 08/09/2017 11:43 AM, Richard Biener wrote:
>> I only have the patch I sent you so I can't re-diff.
>>
>> Richard.
>
> Hi.
>
> I'm sending rebased version of the patch. However the patch
> eats all my memory when e.g. building ../../../libgcc
On Mon, Aug 14, 2017 at 1:23 PM, Richard Biener
wrote:
> On Wed, Aug 9, 2017 at 1:39 PM, Martin Liška wrote:
>> On 08/09/2017 11:43 AM, Richard Biener wrote:
>>> I only have the patch I sent you so I can't re-diff.
>>>
>>> Richard.
>>
>> Hi.
>>
>> I'm sending rebased version of the patch. However
On Mon, Aug 14, 2017 at 1:05 PM, Bin Cheng wrote:
> Hi,
> This patch fixes ICE reported in PR81799. It simply uses is_gimple_val
> rather than is_gimple_condexpr.
> Bootstap and test on x86_64. Is it OK?
I guess this eventually pessimizes code-gen for the case we do not
have the IFN call (even
On Mon, Aug 14, 2017 at 12:21 PM, Richard Biener
wrote:
> On Mon, Aug 14, 2017 at 1:05 PM, Bin Cheng wrote:
>> Hi,
>> This patch fixes ICE reported in PR81799. It simply uses is_gimple_val
>> rather than is_gimple_condexpr.
>> Bootstap and test on x86_64. Is it OK?
>
> I guess this eventually
On Mon, Aug 14, 2017 at 1:25 PM, Richard Biener
wrote:
> On Mon, Aug 14, 2017 at 1:23 PM, Richard Biener
> wrote:
>> On Wed, Aug 9, 2017 at 1:39 PM, Martin Liška wrote:
>>> On 08/09/2017 11:43 AM, Richard Biener wrote:
I only have the patch I sent you so I can't re-diff.
Richard.
On Mon, 14 Aug 2017, Pekka Jääskeläinen wrote:
> Both the inputs and outputs must be flushed to zero in the HSAIL’s
> ‘ftz’ semantics.
Presumably this means that constant folding needs to know about those
semantics, both for operations with a subnormal floating-point argument
(whether or not th
We weren't checking whether the phi in a conditional reduction was
used by the condition itself (which isn't a case we handle).
Tested on aarch64-linux-gnu and x86_64-linux-gnu. OK to install?
Thanks,
Richard
2017-08-11 Richard Sandiford
gcc/
PR tree-optimization/81835
* tr
Hello,
this is a ping for that patch
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00022.html
Thanks.
On Fri, 4 Aug 2017, Richard Biener wrote:
> On Fri, 28 Jul 2017, Jason Merrill wrote:
>
> > On 07/28/2017 05:55 PM, Jason Merrill wrote:
> > > On Fri, Jul 28, 2017 at 8:54 AM, Richard Biener wrote:
> > > > On Tue, 4 Jul 2017, Richard Biener wrote:
> > > >
> > > > > On Tue, 20 Jun 2017, Richard
> On Aug 13, 2017, at 3:41 PM, Martin Sebor wrote:
>
>> --- gcc/config/rs6000/rs6000-c.c (revision 250965)
>> +++ gcc/config/rs6000/rs6000-c.c (working copy)
>> @@ -5812,7 +5812,7 @@ altivec_resolve_overloaded_builtin (location_t loc
>> types. */
>> if (nargs != 2)
>> {
The following patch improves both the speed and code size for 64 bit addition
for RL78:
it emits a library function call instead of emitting code for the 64 bit add
for every single addition.
The addition function which was added in libgcc is hand written, so more
optimal than what GCC generate
Hi,
I'd like to ping this patch, please.
Thanks!
Bill
> On Aug 3, 2017, at 2:34 PM, Bill Schmidt wrote:
>
> Hi,
>
> Here's v2 of the patch with Jakub's suggestions incorporated. Bootstrapped
> and tested on powerpc64le-linux-gnu with no regressions. Is this ok for
> trunk?
>
> Eventually t
On Fri, 2017-08-11 at 12:34 +0200, Torsten Duwe wrote:
> gcc/testsuite/ChangeLog
> 2017-08-11 Torsten Duwe
>
> * c-c++-common/patchable_function_entry-default.c: Skip test on
> ia64.
> * c-c++-common/patchable_function_entry-decl.c: Likewise.
> * c-c++-common/patchable_functio
The thread at https://gcc.gnu.org/ml/gcc/2017-08/msg00090.html discusses
the driver behaviour when OOM kills cc1plus or whatever.
This patch changes the driver so that if the inferior dies via INT,
TERM, QUIT or KILL signals, it emits a clearer message about what happened.
We've been using t
Fix longbranch test so it still generates long tbz branches.
Committed as obvious.
ChangeLog:
2017-08-14 Wilco Dijkstra
gcc/testsuite/
PR target/81643
* gcc.target/aarch64/long_branch_1.c: Improve testcase.
--
diff --git a/gcc/testsuite/gcc.target/aarch64/long_branch_1.c
The trivial tweak below removes the spurious space pointed out
in bug 79998 - typo in diagnostic "specified bound %wu". The
patch has been committed in r251096.
Martin
Index: gcc/gimple-ssa-sprintf.c
===
--- gcc/gimple-ssa-sprintf.
Hello!
Attached patch implements generation of btr, bts and btc instructions.
These insns are generated for operations with registers and exact log2
immediates, where bitpos <= 63 and >= 31. Immediates with bits >= 31
are out of range for x86 andq/orq/xorq instructions, so we save a
movabsq consta
On 08/09/2017 11:00 PM, Jeff Law wrote:
On 08/06/2017 02:07 PM, Martin Sebor wrote:
Part 2 of the series adds attribute nostring to annotate arrays
of and pointers to char with that are intended to store sequences
of characters that aren't necessarily valid (nul-terminated)
strings. In the subs
On Mon, Aug 14, 2017 at 09:21:51AM -0500, Bill Schmidt wrote:
> > On Aug 13, 2017, at 3:41 PM, Martin Sebor wrote:
> >> --- gcc/config/rs6000/rs6000-c.c (revision 250965)
> >> +++ gcc/config/rs6000/rs6000-c.c (working copy)
> >> @@ -5812,7 +5812,7 @@ altivec_resolve_overloaded_builtin (locatio
On Mon, Aug 14, 2017 at 6:17 AM, Richard Biener wrote:
> On Fri, 4 Aug 2017, Richard Biener wrote:
>
>> On Fri, 28 Jul 2017, Jason Merrill wrote:
>>
>> > On 07/28/2017 05:55 PM, Jason Merrill wrote:
>> > > On Fri, Jul 28, 2017 at 8:54 AM, Richard Biener
>> > > wrote:
>> > > > On Tue, 4 Jul 2017,
On Aug 12, 2017, at 9:03 AM, Rainer Orth wrote:
>
> The new gcc.dg/pie-static-[12].c testcases FAIL on several systems:
>
> * Solaris 11.4 has PIE support, but lacks static libc, libm
>
> * Linux without the static libc, libm installed
>
> The following patch fixes this by requiring both PIE a
On Mon, 14 Aug 2017, Martin Sebor wrote:
> I assumed every attribute needed to define an identifier but
> nothing broke after I removed it so it looks like you're right
> variable attributes don't need one. Go figure. It would be
> nice if there was a comment above the block that mentioned that.
On 07/13/2017 02:43 AM, Richard Sandiford wrote:
> Similar to the previous scalar_float_mode patch, but for modes that
> satisfy SCALAR_INT_MODE_P. There are very many uses of scalar integers,
> so this patch only makes a token change to the types of byte_mode,
> word_mode, ptr_mode and rs6000_pmo
On 07/13/2017 02:44 AM, Richard Sandiford wrote:
> This patch adds a POD class for scalar integers, as an instance
> of a new pod_mode template. Later patches will use pod_mode in
> situations that really do need to be POD; this patch is simply
> using PODs to remove load-time initialisation.
>
>
On 07/13/2017 02:44 AM, Richard Sandiford wrote:
> This patch adds a wrapper around mode_for_size for cases in which
> the mode class is MODE_INT (the commonest case). The return type
> can then be an opt_scalar_int_mode instead of a machine_mode.
>
> 2017-07-13 Richard Sandiford
> A
On 07/13/2017 02:45 AM, Richard Sandiford wrote:
> Also use int_mode_for_mode instead of (int_)mode_for_size
> in cases where the requested size was the bitsize of an
> existing mode.
>
> 2017-07-13 Richard Sandiford
> Alan Hayward
> David Sherwood
>
> gcc/
>
On 08/09/2017 10:44 PM, Jeff Law wrote:
On 08/06/2017 02:07 PM, Martin Sebor wrote:
The attached patch adds support for a new GCC format specifier,
G, that behaves like %K but accepts a gcall* argument. This
makes it possible to provide inlining context for "artificial"
inline functions like st
On 08/14/2017 12:09 PM, Joseph Myers wrote:
On Mon, 14 Aug 2017, Martin Sebor wrote:
I assumed every attribute needed to define an identifier but
nothing broke after I removed it so it looks like you're right
variable attributes don't need one. Go figure. It would be
nice if there was a comme
On 07/13/2017 02:45 AM, Richard Sandiford wrote:
> This patch adds a wrapper around smallest_mode_for_size
> for cases in which the mode class is MODE_INT. Unlike
> (int_)mode_for_size, smallest_mode_for_size always returns
> a mode of the specified class, asserting if no such mode exists.
> small
This patch enables the _Float128 keyword for the C langauge all of the time for
PowerPC VSX systems. The __float128 keyword continues to be only enabled if
you use the -mfloat128 option.
A previous patch had separated the underlying support (-mfloat128-type) from
enabling the __float128 keyword (
On 07/13/2017 02:45 AM, Richard Sandiford wrote:
> Replace checks of "GET_MODE_CLASS (...) == MODE_INT" with
> "is_int_mode (..., &var)", in cases where it becomes useful
> to refer to the mode as a scalar_int_mode.
>
> 2017-07-13 Richard Sandiford
> Alan Hayward
> David S
On 07/13/2017 02:46 AM, Richard Sandiford wrote:
> This patch replaces some checks of !VECTOR_MODE_P with checks
> of is_a , in cases where the scalar integer
> modes were the only useful alternatives left.
>
> 2017-07-13 Richard Sandiford
> Alan Hayward
> David Sherwood
On 07/13/2017 02:47 AM, Richard Sandiford wrote:
> This patch replaces some checks against VOIDmode with checks
> of is_a , in cases where scalar integer modes
> were the only useful alternatives left.
>
> gcc/
> 2017-07-13 Richard Sandiford
> Alan Hayward
> David Sherwood
On 07/13/2017 02:47 AM, Richard Sandiford wrote:
> This patch replaces a check against BLKmode with a check
> of is_a , in a case where scalar integer
> modes were the only useful alternatives left.
>
> gcc/
> 2017-07-13 Richard Sandiford
> Alan Hayward
> David Sherwood
On 07/13/2017 02:47 AM, Richard Sandiford wrote:
> Explicitly check for scalar_int_mode in code that maps arithmetic
> to full-mode bit operations. These operations wouldn't work correctly
> for vector modes, for example. In many cases this is enforced also by
> checking whether an operand is CON
On 07/13/2017 02:46 AM, Richard Sandiford wrote:
> This patch replaces checks of "SCALAR_INT_MODE_P (...)" with
> "is_a (..., &var)" in cases where it becomes
> useful to refer to the mode as a scalar_int_mode. It also
> replaces some checks for the two constituent classes (MODE_INT
> and MODE_PA
On Mon, 14 Aug 2017, Martin Sebor wrote:
> /* This header provides a declarative way of describing the attributes
> - that are applied to some functions by default.
> + that are applied to some built-in functions by default. Attributes
> + that apply to types or variables but not functions
On 08/14/2017 01:50 PM, Joseph Myers wrote:
On Mon, 14 Aug 2017, Martin Sebor wrote:
/* This header provides a declarative way of describing the attributes
- that are applied to some functions by default.
+ that are applied to some built-in functions by default. Attributes
+ that apply
Hello, gentle maintainer.
This is a message from the Translation Project robot. (If you have
any questions, send them to .)
A new POT file for textual domain 'gcc' has been made available
to the language teams for translation. It is archived as:
http://translationproject.org/POT-files/gcc-
On 08/07/2017 02:42 AM, Alexander Monakov wrote:
> On Sat, 5 Aug 2017, Richard Sandiford wrote:
>> It would be simpler to test whether targetm.gen_mem_thread_fence
>> returns NULL.
>>
>> This feels a bit hacky though. Checking whether a generator produced no
>> instructions is usually the test for
On 07/13/2017 02:49 AM, Richard Sandiford wrote:
> The *_loc_descriptor routines for clz, popcount, bswap and rotate
> all required SCALAR_INT_MODE_P. This patch moves the checks into
> the caller (mem_loc_descriptor) so that the types of the mode
> parameters can be scalar_int_mode instead of mac
On 07/13/2017 02:49 AM, Richard Sandiford wrote:
> This patch uses is_a in a couple of places that
> were splitting doubleword integer operations into word_mode
> operations. It also uses scalar_int_mode in the expand_expr_real_2
> handling of doubleword shifts.
>
> 2017-07-13 Richard Sandiford
On 07/13/2017 02:48 AM, Richard Sandiford wrote:
> This patch adds is_a checks before load_extend_op/
> LOAD_EXTEND_OP calls, if that becomes useful for later patches.
> (load_extend_op will return UNKNOWN for any other type of mode.)
>
> 2017-07-13 Richard Sandiford
> Alan Hayward
On 07/13/2017 02:50 AM, Richard Sandiford wrote:
> A future patch will make valid_pointer_mode take a scalar_int_mode
> instead of a machine_mode. is_a <...> rather than as_a <...> is
> needed here because we're checking a mode supplied by the user.
>
> 2017-07-13 Richard Sandiford
>
On 07/13/2017 02:50 AM, Richard Sandiford wrote:
> This patch replaces uses of GET_CLASS_NARROWEST_MODE (MODE_INT) with a
> new NARROWEST_INT_MODE macro, which has type scalar_int_mode.
>
> 2017-07-13 Richard Sandiford
> Alan Hayward
> David Sherwood
>
> gcc/
> *
The following patch fixes a performance issue when loading/storing/moving
TImode values when using -mvsx-timode -mcpu=power7 with LRA. The problem is
that the vsx_le_permute_ and vsx_le_perm_{load,store}_ patterns
do no support TImode values in GPRs, and LRA is using these patterns to
fixup constr
On Mon, 14 Aug 2017, Martin Sebor wrote:
> Okay. I expanded on that point in the updated comments below.
>
> Martin
>
> 2017-08-14 Martin Sebor
>
> * builtin-attrs.def: Add comments.
This version is OK.
--
Joseph S. Myers
jos...@codesourcery.com
On 08/10/2017 01:29 PM, Martin Sebor wrote:
diff --git a/gcc/builtins.c b/gcc/builtins.c
index 016f68d..1aa9e22 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
[ ... ]
+
+ if (TREE_CODE (type) == ARRAY_TYPE)
+{
+ /* Return the constant size unless it's zero (that's a
zero-length
+
The undocumented option -mvsx-timode was added because there were reload
bugs we couldn't fix when we tried allowing TImode values in VSX registers.
We used the option to allow TImode values in VSX registers when LRA was
being used, but not when reload was being used. Now that GCC 8 has removed
th
Hi!
Sorry the review took a while.
On Fri, Aug 11, 2017 at 12:28:16PM +0930, Alan Modra wrote:
> * config/rs6000/rs6000.c (rs6000_savres_strategy): Don't restore
> fixed regs.
> diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
> index 74158cd..b628808 100644
> ---
This is exactly the approach that was taken with this patch. An earlier patch
actually contains the patterns that match the truncation:
https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01095.html
-Original Message-
From: Richard Biener [mailto:richard.guent...@gmail.com]
Sent: Monday, Augu
On Fri, Aug 11, 2017 at 12:34:13PM +0930, Alan Modra wrote:
> Bootstrapped and regression tested powerpc64-linux (-m32 too) and
> powerpc64le-linux. OK?
>
> * config/rs6000/rs6000.c (rs6000_reg_live_or_pic_offset_p): Merge..
> (save_reg_p): ..into this. Update all callers.
> (f
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