[PATCH][PR bootstrap/80565] Fixed bootstrap errors due to uninitialized memory

Hi, This patch fixes uninitialized memory errors which caused bootstrap to fail on some distros (e.g. gcc12 on compile farm). This was reported in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80565 (and maybe also https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79224#c15). x86_64 bootstrap completed

Re: [PATCH][PR bootstrap/80565] Fixed bootstrap errors due to uninitialized memory

> Hi, > > This patch fixes uninitialized memory errors which caused bootstrap to > fail on some distros (e.g. gcc12 on compile farm). This was reported > in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80565 (and maybe also > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79224#c15). > > x86_64 boo

Re: [PATCH] Fix PR middle-end/81194, ICE during RTL pass: expand

On Thu, Jun 29, 2017 at 5:01 AM, Peter Bergner wrote: > With the fix to PR51513 and follow on fixes for PR80707, PR80775 and PR80823, > we can now end up with switch statements that contain nothing but a default > case statement. The expand_case() function contains code that assumes we > have at

Re: [PATCH, GCC/ARM] Remove ARMv8-M code for D17-D31

Hi Richard, On 28/06/17 16:56, Richard Earnshaw (lists) wrote: On 20/06/17 16:01, Thomas Preudhomme wrote: Hi, Function cmse_nonsecure_entry_clear_before_return has code to deal with high VFP register (D16-D31) while ARMv8-M Baseline and Mainline both do not support more than 16 double VFP reg

[gomp5] Support OpenMP loops with != condition

Hi! OpenMP 5.0 is going to support loops where condition is not just />= comparison, but also !=, with the requirement that the increment has to be constant expression of 1 or -1 in that case (and no overflow even for unsigned iterators). The following patch implements it, tested on x86_64-linux,

Re: [patch][Ping #3] PR80929: Realistic PARALLEL cost in seq_cost.

On 28.06.2017 22:18, Wilco Dijkstra wrote: Georg-Johann Lay wrote: @@ -5300,6 +5300,9 @@ seq_cost (const rtx_insn *seq, bool spee set = single_set (seq); if (set) cost += set_rtx_cost (set, speed); + else if (INSN_P (seq) + && PARALLEL == GET_CODE (PAT

Re: [PATCH] Fix PR middle-end/81194, ICE during RTL pass: expand

On Thu, Jun 29, 2017 at 10:34 AM, Richard Biener wrote: > On Thu, Jun 29, 2017 at 5:01 AM, Peter Bergner wrote: >> With the fix to PR51513 and follow on fixes for PR80707, PR80775 and PR80823, >> we can now end up with switch statements that contain nothing but a default >> case statement. The e

Re: [C++ Patch] Replace a few more error + error with error + inform

Hi, gently pinging this, still in my tree: On 19/05/2017 18:13, Paolo Carlini wrote: Hi, while looking into some bugs (eg, c++/71464) I noticed a few more of those consecutive errors, which I propose to adjust per the below patchlet. The second case in add_method is a bit tricky because in

[PATCH][OBVIOUS] Fix -mbranch-cost range.

On 06/28/2017 10:14 PM, Rainer Orth wrote: > Hi Martin, > >> On 06/28/2017 06:52 AM, Jeff Law wrote: >>> On 03/15/2017 03:58 AM, Martin Liška wrote: Huh, I forgot to attach the patch. Martin 0001-Introduce-IntegerRange-for-options-PR-driver-79659.patch From

[PATCH] make find_taken_edge handle case with just default

This refactors things a bit to make CFG cleanup handle switches with just a default label. If we make sure to cleanup the CFG after group_case_labels removes cases with just __builtin_unreachable () inside then this fixes the ICE seen in PR81994 as well. I wonder if find_taken_edge should genera

Re: [PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

On Thu, Jun 29, 2017 at 7:06 AM, Hurugalawadi, Naveen wrote: > Hi, > > The code (m1 > m2) * d code should be optimized as m1> m2 ? d : 0. > > The patch optimizes it inside tree-vrp.c when simplifying with the range > inside simplify_stmt_using_ranges. If a multiply is found and either side > has a

[PING^2][PATCH][Aarch64] Relational compare zero not merged into subtract

Ping^2. Original patch posted here: https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00091.html

Re: Tweak BB analysis for dr_analyze_innermost

On Wed, Jun 28, 2017 at 3:36 PM, Richard Sandiford wrote: > dr_analyze_innermost had a "struct loop *nest" parameter that acted > like a boolean. This was added in r179161, with the idea that a > null nest selected BB-level analysis rather than loop analysis. > > The handling seemed strange thoug

[gomp5] Fix taskgroup genericization in Fortran FE

Hi! Apparently I forgot to test fortran last time during the http://gcc.gnu.org/ml/gcc-patches/2017-06/msg00839.html changes. Fixed thusly, committed to gomp-5_0-branch. 2017-06-29 Jakub Jelinek * trans-openmp.c (gfc_trans_omp_taskgroup): Build OMP_TASKGROUP using make_node i

Re: [PATCH PR81196]Analyze ntiers for loop with exit condition comparing induction variables

On Wed, Jun 28, 2017 at 11:32 AM, Bin Cheng wrote: > Hi, > This patch picks up a missed-optimization case in loop niter analysis. With > this > patch, niters information for loop as in added test can be analyzed. > Bootstrap > and test on x86_64 and AArch64. Is it OK? + provided that ei

Re: Avoid generating useless range info

On Wed, Jun 28, 2017 at 9:56 AM, Aldy Hernandez wrote: > > > On 06/27/2017 06:38 AM, Jakub Jelinek wrote: >> >> On Tue, Jun 27, 2017 at 06:26:46AM -0400, Aldy Hernandez wrote: >>> >>> How about this? >> >> >> @@ -360,6 +363,22 @@ set_range_info (tree name, enum value_range_type >> range_type, >>

Re: [arm] Fix incorrect __ARM_ARCH_PROFILE for -march=armv7

On 28/06/17 16:05, Richard Earnshaw (lists) wrote: > ACLE explicitly states that when targetting the common subset of > ARMv7-A, ARMv7-R and ARMv7-M, the __ARM_ARCH_PROFILE macro should not be > set. We currently set it to 'M' which is clearly erroneous. > > The logic for creating this is very co

Re: Tweak BB analysis for dr_analyze_innermost

Richard Biener writes: > On Wed, Jun 28, 2017 at 3:36 PM, Richard Sandiford > wrote: >> dr_analyze_innermost had a "struct loop *nest" parameter that acted >> like a boolean. This was added in r179161, with the idea that a >> null nest selected BB-level analysis rather than loop analysis. >> >>

Re: Tweak BB analysis for dr_analyze_innermost

On Thu, Jun 29, 2017 at 12:32 PM, Richard Sandiford wrote: > Richard Biener writes: >> On Wed, Jun 28, 2017 at 3:36 PM, Richard Sandiford >> wrote: >>> dr_analyze_innermost had a "struct loop *nest" parameter that acted >>> like a boolean. This was added in r179161, with the idea that a >>> nul

[PATCH] Support reduction chain and SLP reduction at the same time

I noticed vect_analyze_slp didn't try SLP reduction when it detected any reduction chain. That's because the LOOP_VINFO_REDUCTIONS array contains also the detected chains -- but a reduction chain can only be vectorized as reduction chain (well, I'm going to fix that! I just ran into this code in

Re: [v2] PR81136: ICE from inconsistent DR_MISALIGNMENTs

On Wed, Jun 28, 2017 at 3:29 PM, Richard Sandiford wrote: > Richard Biener writes: >> On Mon, Jun 26, 2017 at 1:50 PM, Richard Sandiford >> wrote: >>> Richard Biener writes: On Mon, Jun 26, 2017 at 1:14 PM, Richard Sandiford wrote: > I don't think the problem is the lack of a cap

Re: [Ping ^3][PATCH v2] Generate reproducible output independently of the build-path

Dear GCC Global Reviewers, Could any of you please review my patch series? It's about being able to reproducibly build things, even when the build machines are executing the build under different paths. Overview: https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00513.html Full thread, including i

Re: [PATCH] ASAN: handle addressable params (PR sanitize/81040).

On Tue, Jun 20, 2017 at 03:06:56PM +0200, Martin Liška wrote: > +/* Rewrite all usages of tree OP which is a PARM_DECL with a VAR_DECL > + that is it's DECL_VALUE_EXPR. */ > + > +static tree > +rewrite_usage_of_param (tree *op, int *walk_subtrees, void *) > +{ > + if (TREE_CODE (*op) == PARM_DE

Re: Add DR_BASE_ALIGNMENT

On Wed, Jun 28, 2017 at 3:40 PM, Richard Sandiford wrote: > This patch records the base alignment in data_reference, to avoid the > second-guessing that was previously done in vect_compute_data_ref_alignment. > It also makes vect_analyze_data_refs use dr_analyze_innermost, instead > of having an a

Re: [PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

Richard Biener wrote: > Hurugalawadi, Naveen wrote: > > The code (m1 > m2) * d code should be optimized as m1> m2 ? d : 0. > What's the reason of this transform? I expect that the HW multiplier > is quite fast given one operand is either zero or one and a multiplication > is a gimple operation th

[PATCH 1/7] sparc: put bmask* instructions in it's own insn type and adjust DFAs

This patch introduces a new value for the insn type attribute bmask. bmask instructions, which were previously typed as `array', are adapted to use it, and finally the several DFA schedulers are updated accordingly. gcc/ChangeLog: * config/sparc/sparc.md: New instruction type `bmask'.

[PATCH 3/7] sparc: introduce insn subtypes

This patch introduces a new insn attribute `subtype', and marks existing insns appropriately. The resulting instruction hierarchy is documented in a comment. gcc/ChangeLog: * config/sparc/sparc.md ("subtype"): New insn attribute. ("*wrgsr_sp64"): Set insn subtype. ("*rdgs

[PATCH 0/7] Support for the SPARC M8 cpu

This patch serie adds support for the SPARC M8 processor to GCC. The SPARC M8 processor implements the Oracle SPARC Architecture 2017. The first four patches are preparatory work: - bmask* instructions are put in their own instruction type. It makes little sense to have them in the same catego

Re: [PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

On Thu, Jun 29, 2017 at 1:20 PM, Wilco Dijkstra wrote: > Richard Biener wrote: >> Hurugalawadi, Naveen wrote: >> > The code (m1 > m2) * d code should be optimized as m1> m2 ? d : 0. > >> What's the reason of this transform? I expect that the HW multiplier >> is quite fast given one operand is eit

[PATCH 2/7] sparc: put VIS compare instructions in it's own insn type and adjust DFAs

This patch introduces a new value for the insn type attribute viscmp. VIS comparison insn are adapted to use it, and finally the DFA schedulers are updated accordingly. gcc/ChangeLog: * config/sparc/sparc.md ("type"): New insn type viscmp. ("fcmp_vis"): Set insn type to vi

[PATCH 5/7] sparc: basic support for the SPARC M8 cpu

This patch adds the following support for the SPARC M8 cpu, which implements the Oracle SPARC Architecture 2017: - Support for -mcpu=m8 and -mtune=m8. - Definition of cpu target macros and specs in the backend. - Tuning of backend parameters for the M8. - Addition of a new cpu type m8 in the machi

[PATCH 4/7] sparc: reworked M7 DFA based on instruction subtypes

This patch reworks the M7 DFA scheduler to use instruction subtypes. It also removes the v3pipe insn attribute from sparc.md, as it is no longer needed. gcc/ChangeLog: * config/sparc/niagara7.md: Rework the DFA scheduler to use insn subtypes. * config/sparc/sparc.md: Remo

[PATCH 6/7] sparc: support for VIS4B instructions

This patch adds suppport for the following VIS instructions, which are introduced in the Oracle SPARC Architecture 2017 and implemented by the SPARC M8 cpu: - Dictionary unpack. - Partitioned compare with shifted result. - Unsigned partitioned compare with shifted result. - Partitioned dual-equal

[PATCH 7/7] sparc: M8 DFA scheduler

This patch adds a DFA scheduler modelling the core S5 in the SPARC M8 processors. gcc/ChangeLog: * config/sparc/m8.md: New file. * config/sparc/sparc.md: Include m8.md. --- gcc/ChangeLog | 5 + gcc/config/sparc/m8.md| 242

Re: [PATCH v2][ASAN] Implement dynamic allocas/VLAs sanitization.​

Hi! Sorry for the review delay. On Mon, Jun 26, 2017 at 03:49:23PM +0300, Maxim Ostapenko wrote: > (handle_builtin_stackrestore): Likewise. The function is called with _ between stack and restore. > * match.pd: Add new pattern. Unless the patch relies on this, I think it should be

[PATCH] Fix PR81249

Bootstrap and regtest running on x86_64-unknown-linux-gnu. Richard. 2017-06-29 Richard Biener PR tree-optimization/81249 * tree-vect-loop.c (vect_create_epilog_for_reduction): Convert condition reduction result to original scalar type. * g++.dg/torture/pr8124

[committed, PATCH] Add a testcase for PR ipa/80565

The testcase in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80565 is passing now. Check in the testcase and resolve it as fixed. PR ipa/80565 * gcc.dg/torture/pr80565.c: New file. --- gcc/testsuite/ChangeLog| 5 + gcc/testsuite/gcc.dg/torture/pr80565.c | 4

Re: [PATCH, rs6000] Signed builtin support

On Jun 28, 2017, at 4:48 PM, Segher Boessenkool wrote: > > Hi Carl, > > On Wed, Jun 28, 2017 at 08:37:35AM -0700, Carl Love wrote: >> The following patch adds support for the vec_signed, vec_signede, >> vec_signedo and vec_signed2 builtins. > > Are those names ABI-dictated? Unfortunately, yes

Re: [PATCH] Fix PR middle-end/81194, ICE during RTL pass: expand

On 6/29/17 3:51 AM, Richard Biener wrote: > On Thu, Jun 29, 2017 at 10:34 AM, Richard Biener > To answer myself the unreachable case vanishes at > execute_cleanup_cfg_post_optimizing > via group_case_labels. find_taken_edge wouldn't handle this case either. > > I am testing a patch fixing both -

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

> This patch adds a workaround to the Sparc backend for the LEON3FT > store-store errata. It is enabled when using the -mfix-ut699, > -mfix-ut700, or -mfix-gr712rc flag. Let's forget -mfix-gr712rc for now, -mfix-ut700 is enough I think. > The workaround inserts NOP instructions to prevent the fol

Re: [PATCH] Fix pr80044, -static and -pie insanity, and pr81170

Ping? Linux startfile and endfile specs. https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01678.html -- Alan Modra Australia Development Lab, IBM

Re: [PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

On 06/29/2017 05:20 AM, Wilco Dijkstra wrote: > Richard Biener wrote: >> Hurugalawadi, Naveen wrote: >>> The code (m1 > m2) * d code should be optimized as m1> m2 ? d : 0. > >> What's the reason of this transform? I expect that the HW multiplier >> is quite fast given one operand is either zero o

[PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

Hi, This patch series adds support for the ARMv8-R architecture[1] and ARM Cortex-R52[2] to GCC. The patch series consist of the following patches: [ 1/3] Add missing MIDR information for ARM Cortex-R7 and Cortex-R8 processor [ 2/3] Add support for ARMv8-R architecture [ 3/3] Add support for A

[PATCH 1/3, GCC/ARM] Add MIDR info for ARM Cortex-R7 and Cortex-R8

Hi, The driver is missing MIDR information for processors ARM Cortex-R7 and Cortex-R8 to support -march/-mcpu/-mtune=native on the command line. This patch adds the missing information. ChangeLog entry is as follows: *** gcc/ChangeLog *** 2017-01-31 Thomas Preud'homme * config/arm/

Re: [PATCH] make find_taken_edge handle case with just default

On 6/29/17 4:03 AM, Richard Biener wrote: > > This refactors things a bit to make CFG cleanup handle switches with > just a default label. If we make sure to cleanup the CFG after > group_case_labels removes cases with just __builtin_unreachable () > inside then this fixes the ICE seen in PR81994

[PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture

Hi, This patch adds support for ARMv8-R architecture [1] which was recently announced. User level instructions for ARMv8-R are the same as those in ARMv8-A Aarch32 mode so this patch define ARMv8-R to have the same features as ARMv8-A in ARM backend. [1] https://developer.arm.com/products/archi

[PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor

Hi, This patch adds support for the ARM Cortex-R52 processor rencently announced. [1] https://developer.arm.com/products/processors/cortex-r/cortex-r52 ChangeLog entry is as follows: *** gcc/ChangeLog *** 2017-01-31 Thomas Preud'homme * config/arm/arm-cpus.in (cortex-r52): Add new

Re: [PATCH] make find_taken_edge handle case with just default

On Thu, 29 Jun 2017, Peter Bergner wrote: > On 6/29/17 4:03 AM, Richard Biener wrote: > > > > This refactors things a bit to make CFG cleanup handle switches with > > just a default label. If we make sure to cleanup the CFG after > > group_case_labels removes cases with just __builtin_unreachabl

[PATCH] fold_builtin_FUNCTION

I notied the __builtin_FUNCTION () builtin was using raw DECL_NAME, which for C++ dtors and conversion operators gives non-useful names. (no ~ and 'operator N' for N= some int). This patch fixes its folder to use the lang hook that provides a printable name. I did contemplate passing 1 (add sco

Re: [PATCH] make find_taken_edge handle case with just default

On 6/29/17 8:58 AM, Richard Biener wrote: > On Thu, 29 Jun 2017, Peter Bergner wrote: >> Should we offer an early out of group_case_labels_stmt() for the >> fairly common case of new_size == old_size? There's no reason to >> execute the compress labels loop if we didn't combine any of the >> label

[C++ PATCH] whitespace cleanups

A bunch of minor reformatting and cleanups I'd collected. Applied to trunk. nathan -- Nathan Sidwell 2017-06-29 Nathan Sidwell Whitespace cleanups. * call.c (name_as_c_string): Move CONST_CAST to return. (build_new_method_call_1): Remove unneeded bracing. * class.c (include_empty_classes

[C++ PATCH] parser indentation cleanup

This is almost a reformatting diff, converting if (cond) { if (a) A else B } else C into if (!cond) C; else if (a) A else B but it also removes an unnecessary constructor_name assignment: if ( ... constructor_name_p (unqualified_name, class_type)) { unqualified_name = constructor_

Re: [PATCH] make find_taken_edge handle case with just default

On Thu, 29 Jun 2017, Peter Bergner wrote: > On 6/29/17 8:58 AM, Richard Biener wrote: > > On Thu, 29 Jun 2017, Peter Bergner wrote: > >> Should we offer an early out of group_case_labels_stmt() for the > >> fairly common case of new_size == old_size? There's no reason to > >> execute the compress

Re: [PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

On 29 June 2017 at 15:52, Thomas Preudhomme wrote: > Hi, > > This patch series adds support for the ARMv8-R architecture[1] and ARM > Cortex-R52[2] to GCC. The patch series consist of the following patches: Hi Thomas, I think you need to rebase your patch because Richard's recent series changed

Re: [PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

On 29/06/17 15:34, Christophe Lyon wrote: On 29 June 2017 at 15:52, Thomas Preudhomme wrote: Hi, This patch series adds support for the ARMv8-R architecture[1] and ARM Cortex-R52[2] to GCC. The patch series consist of the following patches: Hi Thomas, I think you need to rebase your patch b

[C++ PATCH] constructor_name

This cleans up constructor_name use. I use constructor_name when checking for ctor/dtor type things and DECL_NAME (TYPE_NAME (X)) when dealing with a class's self reference. IMHO these are conceptually different, even if we might end up with the same identifier in the end. 1) check_dtor_name

[C++ PATCH] maybe_add_lang_type_raw simplification

I found maybe_add_lang_type_raw benefitted from simply returning false early, rather than use a bool flag. applied to trunk. nathan -- Nathan Sidwell 2017-06-29 Nathan Sidwell * lex.c (maybe_add_lang_type_raw): Exit early, rather than use a flag. Index: lex.c

[C++ PATCH] special identifiers

We currently #define a bunch of names in cp-tree.h, never override them, and then use them exactly once during initialization. I think these were hold-overs from when changing from the old to new ABI. Anyway, I see no reason for the indirection. I also renamed the cdtor variant names to be c

Re: [PING][PATCH] Move the check for any_condjump_p from sched-deps to target macros

On 06/26/2017 10:19 PM, Hurugalawadi, Naveen wrote: > Hi Jeff, > > Thanks for the review and your approval for final patch. > Sorry, It was a long weekend and hence could not revert to your > comments earlier. > >>> You need a ChangeLog entry, but I think that's it. Can you >>> please repost wit

Re: [PATCH] Transform (m1 > m2) * d into m1> m2 ? d : 0

Richard Biener wrote: > int f (int m, int c) > { >  return (m & 1) * c; > } This case (integer[0,1] rather than boolean input) should be transformed into c & -(m & 1). Wilco

Re: [PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

On 29 June 2017 at 16:37, Thomas Preudhomme wrote: > On 29/06/17 15:34, Christophe Lyon wrote: >> >> On 29 June 2017 at 15:52, Thomas Preudhomme >> wrote: >>> >>> Hi, >>> >>> This patch series adds support for the ARMv8-R architecture[1] and ARM >>> Cortex-R52[2] to GCC. The patch series consist

Re: [PATCH 2/3, GCC/ARM] Add support for ARMv8-R architecture

Please ignore this patch. I'll respin the patch on a more recent GCC. Best regards, Thomas On 29/06/17 14:55, Thomas Preudhomme wrote: Hi, This patch adds support for ARMv8-R architecture [1] which was recently announced. User level instructions for ARMv8-R are the same as those in ARMv8-A Aa

Re: [PATCH 3/3, GCC/ARM] Add support for ARM Cortex-R52 processor

Please ignore this patch. I'll respin the patch on a more recent GCC. Best regards, Thomas On 29/06/17 14:56, Thomas Preudhomme wrote: Hi, This patch adds support for the ARM Cortex-R52 processor rencently announced. [1] https://developer.arm.com/products/processors/cortex-r/cortex-r52 Chan

libgo patch committed: Fixes for go tool for other build modes

This libgo patch fixes the go tool when using -buildmode={c-archive,c-shared,pie} with gccgo. The tests are misc/cgo tests that are not currently run but will be run soon. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

Hello Eric, Thank you for reviewing the patch. Let's forget -mfix-gr712rc for now, -mfix-ut700 is enough I think. I think it would be confusing to use the -mfix-ut700 flag when compiling for the GR712RC. Now when we are not using a generic name for the errata workaround we should at least h

libgo patch committed: Fix testcarchive to work with gccgo

This patch fixes the misc/cgo/testcachive test to work with gccgo. This test is not currently run, but it will be soon. Bootstrapped on x86_64-pc-linux-gnu. Committed to mainline. Ian Index: gcc/go/gofrontend/MERGE === --- gcc/go/go

C++ PATCH for c++/81164, ICE with invalid inherited constructor

It's ill-formed to inherit a constructor from an indirect base, but we were failing to catch that for virtual bases, whose binfos look like direct bases. Tested x86_64-pc-linux-gnu, applying to trunk. commit b8d3d6f1932db56d61c522bcdcff5142b307e23c Author: Jason Merrill Date: Thu Jun 29 11:06:0

Re: [Doc, AArch64] Fix/Update AArch64 options.

On 06/28/2017 01:28 AM, Yvan Roux wrote: Hi Sandra, [snip] OK, here is the new patch with the comments addressed. I've spotted that there is also some m / -mno options at least in the ARM section, I'll make another patch to fix that. This version looks fine. Thanks for taking care of this!

Re: [Doc, AArch64] Fix/Update AArch64 options.

On 28/06/17 08:28, Yvan Roux wrote: > Hi Sandra, > > On 27 June 2017 at 18:05, Sandra Loosemore wrote: >> On 06/27/2017 06:19 AM, Yvan Roux wrote: >> >>> diff --git a/gcc/config/aarch64/aarch64.opt >>> b/gcc/config/aarch64/aarch64.opt >>> index 942a7d5..0fd1bfa 100644 >>> --- a/gcc/config/aarch64

Re: [PATCH, VAX] Correct ffs instruction constraint

Ping. On Tue, Jun 20, 2017 at 08:05:42PM +, co...@sdf.org wrote: > VAX' FFS as variable-length bit field instruction uses a "base" > operand of type "vb" meaning "byte address". > "base" can be 32 bits (SI) and due to the definition of > ffssi2/__builtin_ffs() with the operand constraint "m",

Re: [PATCH rs6000] remove implicit static var outputs of toc_relative_expr_p

On Wed, 2017-06-28 at 18:19 -0500, Segher Boessenkool wrote: > On Wed, Jun 28, 2017 at 03:21:49PM -0500, Aaron Sawdey wrote: > > -toc_relative_expr_p (const_rtx op, bool strict) > > +toc_relative_expr_p (const_rtx op, bool strict, const_rtx > > *tocrel_base_ret, > > +  const_rtx *tocr

[PATCH] Use a specfile that actually allows building programs on NetBSD

I was thinking of holding a party for the upcoming one year anniversary of pinging this patch, that was committed to NetBSD's copy of GCC about a decade ago. without it, I can't compile simple programs. --- gcc/config/netbsd.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/config/netbsd

[PATCH] Fix PR77765

PR77765 exposed an ICE triggered in gfortran's acc routine parser by an uninitialized proc_name. That situation occurred because the function containing the acc routine directive has an error, so gfc_current_ns->proc_name was never set. Although it could be argued that the acc routine parser shoul

Re: C/C++ PATCH to add __typeof_noqual (PR c/65455, c/39985)

On Wed, 28 Jun 2017, Martin Sebor wrote: > > The more limited interfaces could, of course, be __typeof_noqual in some > > form. > > Actually, despite what I've been arguing, I agree. I've come > to realize that what makes me uneasy about it is its name: it > makes it sound like a special purpose

gotools patch committed: Test runtime, misc/cgo/{test,testcarchive}

This patch to the gotools Makefile adds tests to `make check`. We now test the runtime package using the newly built go tool, and test that cgo works by running the misc/cgo/test and misc/cgo/testcarchive tests. Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed to mainline. Ian

Re: [PATCH] Use a specfile that actually allows building programs on NetBSD

On Thu, 29 Jun 2017, coypu wrote: > I was thinking of holding a party for the upcoming one year anniversary > of pinging this patch, that was committed to NetBSD's copy of GCC about > a decade ago. without it, I can't compile simple programs. I advise CC:ing the listed NetBSD maintainers (Jason T

Re: [PATCH-v3] [SPARC] Add a workaround for the LEON3FT store-store errata

From: Daniel Cederman Date: Thu, 29 Jun 2017 17:15:43 +0200 >> I'm not thrilled with this, it's undocumented, the other workaround >> don't have >> it and I don't think that we really need it. > > The B2BST errata workaround requires more changes to assembler > routines commonly used by operatin

Re: [PATCH] warn on mem calls modifying objects of non-trivial types (PR 80560)

Hello, > diff --git a/gcc/hash-table.h b/gcc/hash-table.h > index 0f7e21a..443d16c 100644 > --- a/gcc/hash-table.h > +++ b/gcc/hash-table.h > @@ -803,7 +803,10 @@ hash_table::empty_slow () >m_size_prime_index = nindex; > } >else > -memset (entries, 0, size * sizeof (value_type)

Re: C/C++ PATCH to add __typeof_noqual (PR c/65455, c/39985)

On 06/29/2017 09:56 AM, Joseph Myers wrote: On Wed, 28 Jun 2017, Martin Sebor wrote: The more limited interfaces could, of course, be __typeof_noqual in some form. Actually, despite what I've been arguing, I agree. I've come to realize that what makes me uneasy about it is its name: it makes

Re: [PATCH, GCC/ARM, 0/3] Add support for ARMv8-R

On 29/06/17 16:12, Christophe Lyon wrote: On 29 June 2017 at 16:37, Thomas Preudhomme Why do you link armv8-r architecture definition to cortex-r4? I understand, where did I do such a thing? In patch #2 you have: diff --git a/gcc/config/arm/arm-cpu-data.h b/gcc/config/arm/arm-cpu-data.h

[PATCH] Fix vec_extract_lo_* patterns (PR target/81225)

Hi! This patch fixes various issues with the vec_extract_lo_* patterns. There are splitters for these, but only for some cases (no mask, and in one case also not xmm32+ reg) that change those into just a copy or load of the low part subreg, but if those can't be used, the vextract* insns don't acc

Re: [PATCH] Call BUILT_IN_ASAN_HANDLE_NO_RETURN before BUILT_IN_UNWIND_RESUME (PR sanitizer/81021).

On 06/13/2017 02:09 AM, Martin Liška wrote: > Hi. > > For a function that does not handle an expection (and calls > BUILT_IN_UNWIND_RESUME), > we need to emit call to BUILT_IN_ASAN_HANDLE_NO_RETURN. That will clean up > stack > which can possibly contain poisoned shadow memory that will not be c

[PATCH 1/2] combine: Print insns with the cost dump

In the combine dump file, at the start there is a list of the RTL cost of every insn. The only thing listed about the insns is the UID though. To make it more useful, this patch prints the insn itself as well (in slim format). Tested on powerpc64-linux {-m32,-m64}, committing to trunk Segher

[PING*3, Ada] Re: Handle data dependence relations with different bases

Ping*3 Richard Sandiford writes: > Ping*2 > > Richard Sandiford writes: >> Ping for this Ada patch/question. >> >> Richard Sandiford writes: >>> Richard Biener writes: >> How does this look? Changes since v1: >> >> - Added access_fn_component_p to check for valid access function >

Re: libdecnumber/bid/bid2dpd_dpd2bid.c: Simplify code

On 05/26/2017 07:34 AM, Sylvestre Ledru wrote: > Hello, > > The attach patch (dup.diff) performs the following changes: > > * bid/bid2dpd_dpd2bid.c: Remove identical code for different > branches (CID 1286836, 1286837, 1286838) > Remove some useless } else { declaration as we ar

Re: [PATCH] Fix PR77765

On Thu, Jun 29, 2017 at 08:54:54AM -0700, Cesar Philippidis wrote: > PR77765 exposed an ICE triggered in gfortran's acc routine parser by an > uninitialized proc_name. That situation occurred because the function > containing the acc routine directive has an error, so > gfc_current_ns->proc_name wa

Re: PR80806

On 05/23/2017 09:58 AM, Martin Sebor wrote: > On 05/18/2017 12:55 PM, Prathamesh Kulkarni wrote: >> Hi, >> The attached patch tries to fix PR80806 by warning when a variable is >> set using memset (and friends) but not used. I chose to warn in dse >> pass since dse would detect if the variable pass

Re: PR80806

On 06/29/2017 11:57 AM, Jeff Law wrote: > On 05/23/2017 09:58 AM, Martin Sebor wrote: >> On 05/18/2017 12:55 PM, Prathamesh Kulkarni wrote: >>> Hi, >>> The attached patch tries to fix PR80806 by warning when a variable is >>> set using memset (and friends) but not used. I chose to warn in dse >>> p

Re: PR80806

On 05/18/2017 12:55 PM, Prathamesh Kulkarni wrote: > Hi, > The attached patch tries to fix PR80806 by warning when a variable is > set using memset (and friends) but not used. I chose to warn in dse > pass since dse would detect if the variable passed as 1st argument is > a dead store. Does this ap

[PR c++/81247] ICE with bogus input

This fixes 81247. There are two parts, firstly it seems pointless to parse try and parse a namespace body when there's a missing '{'. I changed the parser to immediately close the new namespace and return in that case. However, the bug is in my updated do_pushdecl handling. When the incom

Re: [PATCH/AARCH64] Improve aarch64 conditional compare usage

On Tue, 2017-06-27 at 16:45 -0600, Jeff Law wrote: > > +  /* If we have a boolean variable allow it and generate a compare > > + to zero reg when expanding.  */ > > +  if (!g) > > +return (TREE_CODE (TREE_TYPE (t)) == BOOLEAN_TYPE); > Depending on how you use T, you might be better off che

Re: [PATCH] Fold (a > 0 ? 1.0 : -1.0) into copysign (1.0, a) and a * copysign (1.0, a) into abs(a)

On Sun, Jun 25, 2017 at 2:28 PM, Andrew Pinski wrote: > On Sun, Jun 25, 2017 at 11:18 AM, Andrew Pinski wrote: >> On Sun, Jun 25, 2017 at 1:28 AM, Marc Glisse wrote: >>> +(for cmp (gt ge lt le) >>> + outp (convert convert negate negate) >>> + outn (negate negate convert convert) >>> + /*

Small tweak to RTL expansion of some array accesses on RISC targets

I noticed that, when a variable-sized object declared on the stack turns out to be of fixed size, the optimizer can replace the call to __builtin_alloca by the declaration of fixed-size local array. Now, even if the alignment of the object is explicitly preserved, the alignment of its type is n

C++ PATCH for c++/81188, error matching decltype of member function call

Here, cp_tree_equal was assuming that the member operand of COMPONENT_REF will be == if it is equivalent; that isn't accurate for a reference to a member function. So let's remove the special case and fall back on normal expression handling. Tested x86_64-pc-linux-gnu, applying to trunk and 7. co

Re: [PATCH, VAX] Correct ffs instruction constraint

On 06/29/2017 09:47 AM, co...@sdf.org wrote: > Ping. > > On Tue, Jun 20, 2017 at 08:05:42PM +, co...@sdf.org wrote: >> VAX' FFS as variable-length bit field instruction uses a "base" >> operand of type "vb" meaning "byte address". >> "base" can be 32 bits (SI) and due to the definition of >> f

[PATCH] [PR 81245] Fix tree-if-conv calling of update_stmt after fold_stmt

Hi, As described in the bug, tree-if-conv is calling update_stmt on an old stmt which might have been removed from the IR already (transforming of an assignment to a call in this case). This fixes the problem by calling update_stmt on the new statement that fold_stmt might have created. OK? Bo

Re: [PATCH] warn on mem calls modifying objects of non-trivial types (PR 80560)

On 06/29/2017 10:15 AM, Jan Hubicka wrote: Hello, diff --git a/gcc/hash-table.h b/gcc/hash-table.h index 0f7e21a..443d16c 100644 --- a/gcc/hash-table.h +++ b/gcc/hash-table.h @@ -803,7 +803,10 @@ hash_table::empty_slow () m_size_prime_index = nindex; } else -memset (entries, 0

Re: [PATCH] PR target/80556

On 28 Jun 2017, at 18:40, Jeff Law wrote: > > On 06/09/2017 07:57 AM, Simon Wright wrote: >>2017-06-09 Simon Wright >> >>PR target/80556 >>* configure.ac (stage1_ldflags): For Darwin, include -lSystem. >> (poststage1_ldflags): likewise. >>* configure: re

C++ PATCH for c++/81180, ICE with C++17 member class template deduction

The substitution we do in build_deduction_guide needs processing_template_decl set, since it's only partial instantiation, and also needs to be done on the template; substituting the FUNCTION_DECL pattern doesn't properly adjust the template parameters on the template, which we will use in building

[PATCH] Add RDMA support to Falkor.

Falkor is an ARMV8-A part, but also includes the RDMA extension from ARMV8.1-A. I'd like to enable support for the RDMA instructions when -mcpu=falkor is used, and also make the RDMA intrisics available. To do that, I need to add rdma as an architecture extension, and modify a few things to use it

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