Hi,
This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This
specific patch factors out the checks for MOVW/MOVT availability and whether to
use it. To this end, the new macro TARGET_HAVE_MOVT is introduced and code is
modified to use it or the existing TARGET_USE_MOVT as
Hi!
On Tue, 15 Dec 2015 17:44:59 +0100, I wrote:
> On Wed, 9 Dec 2015 17:56:13 +0800, "Thomas Preud'homme"
> wrote:
> > c-c++-common/attr-simd-3.c fails to compile on arm-none-eabi targets due to
> > -fcilkplus needing -pthread which is not available for those targets. This
> > patch solves th
Hi,
We decided to apply the following patch to the ARM embedded 5 branch.
Best regards,
Thomas
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Thursday, December 17, 2015 3:59 PM
> To: gcc-patch
Hi,
This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This
specific patch makes the compiler start generating code with the new MOVT/MOVW
instructions for ARMv8-M Baseline.
[1] For a quick overview of ARMv8-M please refer to the initial cover letter.
ChangeLog entry is
Hi,
We decided to apply the following patch to the ARM embedded 5 branch.
Best regards,
Thomas
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Thursday, December 17, 2015 4:08 PM
> To: gcc-patch
Hi,
This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This
specific patch makes the compiler start generating code with the new CB(N)Z and
(U|S)DIV instructions for ARMv8-M Baseline.
Sharing of instruction patterns for div insn template with ARM or Thumb-2 was
done by
Hi,
We decided to apply the following patch to the ARM embedded 5 branch.
Best regards,
Thomas
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Thursday, December 17, 2015 4:18 PM
> To: gcc-patch
On Thu, Dec 17, 2015 at 09:02:39AM +0100, Thomas Schwinge wrote:
> On Tue, 15 Dec 2015 17:44:59 +0100, I wrote:
> > On Wed, 9 Dec 2015 17:56:13 +0800, "Thomas Preud'homme"
> > wrote:
> > > c-c++-common/attr-simd-3.c fails to compile on arm-none-eabi targets due
> > > to -fcilkplus needing -pthre
Hi,
> From: Jakub Jelinek [mailto:ja...@redhat.com]
> Sent: Thursday, December 17, 2015 4:26 PM
> > >
> > > > --- a/gcc/testsuite/lib/target-supports.exp
> > > > +++ b/gcc/testsuite/lib/target-supports.exp
> > > > @@ -1432,7 +1432,12 @@ proc check_effective_target_cilkplus { } {
> > > > if {
Reverted now.
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Wednesday, December 09, 2015 5:56 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH, testsuite] Fix PR68629: attr-simd-3.c failure on
On Dec 16, 2015, at 11:29 PM, Rainer Orth wrote:
> Here's what I came up with. Tested with the appropriate runtest
> invocations both in a tree with the Xcode 7/LLVM as without stabs
> support, where the tests come out UNSUPPORTED, and another one with the
> Xcode 6.4/gas as with stabs, where the
Hi all,
This patchset fixes bugs in comparison functions used in qsort(3).
Standard requires comparison functions to satisfy certain
symmetry/transitivity axioms ("total ordering" in
http://pubs.opengroup.org/onlinepubs/009695399/functions/qsort.html).
Violation triggers undefined behavior wh
Some obvious symmetry fixes.
Cc-ing
* Andrey (Belevantsev) for bb_top_order_comparator
* Andrew (MacLeod) for compare_case_labels
* Andrew (Pinski) for resort_field_decl_cmp
* Diego for pair_cmp
* Geoff for resort_method_name_cmp
* Jakub for compare_case_labels
* Jason for method_name_cmp
* Richa
On 16/12/15 00:15, Andrew Burgess wrote:
This is a collection of 4 bug fix patches for arc. All 4 patches are
really stand-alone, I've only grouped them together as they all only
effect arc.
Note for future postings: ChangeLog entries are supposed to appear as
plain text, not as diff.
On Wed, Dec 16, 2015 at 8:22 PM, Jan Hubicka wrote:
> Hi,
> I checked the ipa-pta and pta implementations and these seems to work just
> fine with presence of aliases because get_constraint_for_ssa_var already
> looks into the alias targets.
>
> This patch adds a testcase I constructed. Since I a
Some more symmetry fixes. These were detected manually (not via
automatic analysis by SortChecker)
so I've put them to a separate patch.
Cc-ing
* Alexandre for sel_rank_for_schedule
* Ben for cmp_modes
* Jakub for range_entry_cmp
* Richard for sort_bbs_in_loop_postorder_cmp,
sort_locs_in_loop_
This patch fixes intransitive comparison in reload_pseudo_compare_func.
Imagine the following
situation:
1) bitmap_bit_p is unset for A and B but set for C
2) A < B (due to early ira_reg_class_max_nregs comparison)
3) B < C (due to following regno_assign_info comparison)
It may then easily happe
Another intransitive comparison in reload_pseudo_compare_func. Buggy
scenario:
1) A and B are ints of equal presion so we return 0
2) C is REAL and thus can compare differently to A and B
Cc-ing Martin who's the original author.
/Yury
>From 6f3930ad81945f6b5d7aecfdda16089547a592d3 Mon Sep 17 00
That's an interesting one. The original comparison function assumes that
operand_equal_p(a,b) is true iff compare_tree(a, b) == 0.
Unfortunately that's not true (functions are written by different authors).
This causes subtle violation of transitiveness.
I believe removing operand_equal_p should
On 16/12/15 00:15, Andrew Burgess wrote:
Missing function declaration causes a warning, that results in test
failure.
Ah, this test was affected when the default language was changed to
gnu11 in October last year.
gcc/testsuite/ChangeLog:
* gcc.target/arc/jump-around-jump.c (rtc_set
Richard,
Here is modified patch which checks only that exit block belongs to loop.
Bootstrapping and regression testing were successful.
Is it OK for trunk?
ChangeLog:
2014-12-17 Yuri Rumyantsev
PR tree-optimization/68906
* tree-ssa-loop-unswitch.c (tree_unswitch_outer_loop): Add a check
th
Hi,
We decided to apply the following patch to the ARM embedded 5 branch.
Best regards,
Thomas
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Wednesday, December 16, 2015 7:56 PM
> To: gcc-patc
Hi,
We decided to apply the following patch to the ARM embedded 5 branch.
Best regards,
Thomas
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Wednesday, December 16, 2015 7:59 PM
> To: gcc-patc
Hi,
We decided to apply the following patch to the ARM embedded 5 branch.
Best regards,
Thomas
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Thomas Preud'homme
> Sent: Wednesday, December 16, 2015 8:04 PM
> To: 'Ramana
Hi,
This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This
specific patch enable atomics for ARMv8-M Mainline. No change is needed to
existing patterns since Thumb-2 backend can already handle them fine.
[1] For a quick overview of ARMv8-M please refer to the initial co
On 16/12/15 17:28, Jeff Law wrote:
On 12/16/2015 10:00 AM, Kyrill Tkachov wrote:
On 16/12/15 12:18, Bernd Schmidt wrote:
On 12/15/2015 05:21 PM, Kyrill Tkachov wrote:
Then for the shift pattern in the MD file we'd have to
dynamically select the scheduling type depending on whether or
not the
Hi,
the attached patch renames the constm1_operand predicate to
all_ones_operand and introduces a check for int mode.
It should be applied on top of the last patch ([Patch] S/390: Simplify
vector conditionals).
Regtested on s390.
Regards
Robin
gcc/ChangeLog:
2015-12-15 Robin Dapp
*
On 16/12/15 17:06, Jeff Law wrote:
On 12/04/2015 05:39 AM, Szabolcs Nagy wrote:
As described in pr other/67627, the all-multi target can be
built in parallel with the %_.lo targets which generate make
dependencies that are parsed during the build of all-multi.
gcc -MD does not generate the make
Bootstrapped on x86_64-unknown-linux-gnu, applied.
Richard.
2015-12-16 Richard Biener
* gimple-ssa.h (struct gimple_df): Remove modified_noreturn_calls
field.
* tree-ssa.c (delete_tree_ssa): Do not zero it.
Index: gcc/gimple-ssa.h
On Thu, Dec 17, 2015 at 12:29 AM, H.J. Lu wrote:
> Since sibcall never returns, we can only use call-clobbered register
> as GOT base. Otherwise, callee-saved register used as GOT base won't
> be properly restored.
>
> Tested on x86-64 with -m32. OK for trunk?
You don't have to add explicit clo
Hi,
On 16/12/2015 23:10, Patrick Palka wrote:
gcc/cp/ChangeLog:
PR c++/59878
* typeck.c (convert_for_initialization): Don't perform an early
decaying conversion if converting to a class type.
gcc/testsuite/ChangeLog:
PR c++/59878
* g++.dg/conversion/pr59878.C: New test.
Ni
On 16/12/15 00:15, Andrew Burgess wrote:
* config/arc/arc.md (*loadqi_update): Use 'memory_operand' and fix
RTL pattern to include the plus.
(*load_zeroextendqisi_update): Likewise.
(*load_signextendqisi_update): Likewise.
(*loadhi_update): Likewise.
This patch adds support for loading vector 16bit floating point immediates
(modes V*HF) using a movi instruction. We leverage the existing code that does
checking for an 8 bit pattern in a 64/128-bit long splattered version of the
concatenated bit pattern representations of the individual constant
On 16/12/15 15:01, Richard Biener wrote:
The following patch adds a heuristic to prefer store/load-lanes
over SLP when vectorizing. Compared to the variant attached to
the PR I made the STMT_VINFO_STRIDED_P behavior explicit (matching
what you've tested).
Not sure I follow this. Compared to t
Hello Jeff and Richard:
Here is the Summary of the FDO(Feedback Directed Optimization ) performance
results.
SPEC CPU2000 INT benchmarks.
a) FDO + Splitting Paths enabled + tracer enabled
Geomean Score = 3907.751673.
b) FDO + No Splitting Paths + tracer enabled
Geomean Score = 3895.191
On Thu, 17 Dec 2015, Alan Lawrence wrote:
> On 16/12/15 15:01, Richard Biener wrote:
> >
> > The following patch adds a heuristic to prefer store/load-lanes
> > over SLP when vectorizing. Compared to the variant attached to
> > the PR I made the STMT_VINFO_STRIDED_P behavior explicit (matching
>
On 16/12/15 00:15, Andrew Burgess wrote:
gcc/ChangeLog:
* config/arc/arc.c (arc_loop_hazard): Don't convert the jump label
rtx to an rtx_insn until we confirm it's not a return rtx.
gcc/testsuite/ChangeLog:
* gcc.target/arc/loop-hazard-1.c: New file.
Thanks, I've
On Wed, 16 Dec 2015, Jakub Jelinek wrote:
> Hi!
>
> As can be seen on the testcases below, on > 64 bit precision bitfields
> we either ICE or miscompile.
>
> get_int_cst_ext_nunits already has code that for unsigned precision
> in multiplies of HOST_BITS_PER_WIDE_INT it forces TREE_INT_CST_EXT_N
On Thu, Dec 17, 2015 at 11:58:30AM +0300, Yury Gribov wrote:
> 2015-12-17 Yury Gribov
>
> * c-family/c-common.c (resort_field_decl_cmp):
> Make symmteric.
> * cp/class.c (method_name_cmp): Ditto.
> (resort_method_name_cmp): Ditto.
> * fortran/interface.c (pair_cmp)
On Thu, 17 Dec 2015, Yury Gribov wrote:
> Some obvious symmetry fixes.
>
> Cc-ing
> * Andrey (Belevantsev) for bb_top_order_comparator
> * Andrew (MacLeod) for compare_case_labels
> * Andrew (Pinski) for resort_field_decl_cmp
> * Diego for pair_cmp
> * Geoff for resort_method_name_cmp
> * Jakub f
On 10 September 2015 at 12:28, Jiong Wang wrote:
>
> TLS instruction sequences are always with fixed format, there is no need
> to use operand modifier, we can hardcode the relocation modifiers into
> instruction pattern, all those redundant checks in aarch64_print_operand
> can be removed.
>
> OK
On 12/17/2015 02:41 PM, Richard Biener wrote:
On Thu, 17 Dec 2015, Yury Gribov wrote:
Some obvious symmetry fixes.
Cc-ing
* Andrey (Belevantsev) for bb_top_order_comparator
* Andrew (MacLeod) for compare_case_labels
* Andrew (Pinski) for resort_field_decl_cmp
* Diego for pair_cmp
* Geoff for r
On Thu, Dec 17, 2015 at 12:33:22PM +0100, Richard Biener wrote:
> > @@ -1245,11 +1245,9 @@ static unsigned int
> > get_int_cst_ext_nunits (tree type, const wide_int &cst)
> > {
> >gcc_checking_assert (cst.get_precision () == TYPE_PRECISION (type));
> > - /* We need an extra zero HWI if CST i
On Thu, 17 Dec 2015, Yury Gribov wrote:
> That's an interesting one. The original comparison function assumes that
> operand_equal_p(a,b) is true iff compare_tree(a, b) == 0.
> Unfortunately that's not true (functions are written by different authors).
>
> This causes subtle violation of transiti
On Thu, Dec 17, 2015 at 02:47:29PM +0300, Yury Gribov wrote:
> On 12/17/2015 02:41 PM, Richard Biener wrote:
> >On Thu, 17 Dec 2015, Yury Gribov wrote:
> >
> >>Some obvious symmetry fixes.
> >>
> >>Cc-ing
> >>* Andrey (Belevantsev) for bb_top_order_comparator
> >>* Andrew (MacLeod) for compare_case
Hello,
On 17.12.2015 11:58, Yury Gribov wrote:
Some obvious symmetry fixes.
Cc-ing
* Andrey (Belevantsev) for bb_top_order_comparator
Here, as Jakub mentioned, we assume that the argument addresses will never
be equal, thus that would always be different basic blocks (the comparator
is used
On Thu, 17 Dec 2015, Yury Gribov wrote:
> On 12/17/2015 02:41 PM, Richard Biener wrote:
> > On Thu, 17 Dec 2015, Yury Gribov wrote:
> >
> > > Some obvious symmetry fixes.
> > >
> > > Cc-ing
> > > * Andrey (Belevantsev) for bb_top_order_comparator
> > > * Andrew (MacLeod) for compare_case_labels
On Thu, 17 Dec 2015, Jakub Jelinek wrote:
> On Thu, Dec 17, 2015 at 12:33:22PM +0100, Richard Biener wrote:
> > > @@ -1245,11 +1245,9 @@ static unsigned int
> > > get_int_cst_ext_nunits (tree type, const wide_int &cst)
> > > {
> > >gcc_checking_assert (cst.get_precision () == TYPE_PRECISION
Hi!
On Wed, 16 Dec 2015 15:42:55 +0100, Tom de Vries wrote:
> On 16/12/15 14:16, Richard Biener wrote:
> > On Mon, 14 Dec 2015, Tom de Vries wrote:
> >
> >> On 14/12/15 14:26, Richard Biener wrote:
> >>> On Sun, 13 Dec 2015, Tom de Vries wrote:
> This patch:
> - moves the kernels pass g
On Thu, Dec 17, 2015 at 10:21 AM, Yuri Rumyantsev wrote:
> Richard,
>
> Here is modified patch which checks only that exit block belongs to loop.
>
> Bootstrapping and regression testing were successful.
> Is it OK for trunk?
Ok with the spurious
@@ -441,7 +441,7 @@
iterations = estimated_loo
On 12/17/2015 02:39 PM, Jakub Jelinek wrote:
On Thu, Dec 17, 2015 at 11:58:30AM +0300, Yury Gribov wrote:
2015-12-17 Yury Gribov
* c-family/c-common.c (resort_field_decl_cmp):
Make symmteric.
* cp/class.c (method_name_cmp): Ditto.
(resort_method_name_cmp): Dit
Hi,
Consider this patch, which reduces max_len of the oacc function
attribute to 0:
...
diff --git a/gcc/fortran/f95-lang.c b/gcc/fortran/f95-lang.c
index 8556b70..60f4ad3 100644
--- a/gcc/fortran/f95-lang.c
+++ b/gcc/fortran/f95-lang.c
@@ -93,7 +93,7 @@ static const struct attribute_spec gfc_a
On 12/17/2015 02:58 PM, Andrey Belevantsev wrote:
Hello,
On 17.12.2015 11:58, Yury Gribov wrote:
Some obvious symmetry fixes.
Cc-ing
* Andrey (Belevantsev) for bb_top_order_comparator
Here, as Jakub mentioned, we assume that the argument addresses will
never be equal,
The problem is that t
On 12/17/2015 02:59 PM, Richard Biener wrote:
On Thu, 17 Dec 2015, Yury Gribov wrote:
On 12/17/2015 02:41 PM, Richard Biener wrote:
On Thu, 17 Dec 2015, Yury Gribov wrote:
Some obvious symmetry fixes.
Cc-ing
* Andrey (Belevantsev) for bb_top_order_comparator
* Andrew (MacLeod) for compare_c
Hi,
I've noticed that this patch has been applied only on trunk and not on
the gcc-5-branch. Is it a problem to include EVENTS in gcc-5?
2015-12-02 23:00 GMT+01:00 Steve Kargl :
> Committed as revision 231208.
>
> Alessandro, Tobias, is this a candidate for a commit to
> the 5-branch when it is r
On Thu, 17 Dec 2015, Yury Gribov wrote:
> On 12/17/2015 02:59 PM, Richard Biener wrote:
> > On Thu, 17 Dec 2015, Yury Gribov wrote:
> >
> > > On 12/17/2015 02:41 PM, Richard Biener wrote:
> > > > On Thu, 17 Dec 2015, Yury Gribov wrote:
> > > >
> > > > > Some obvious symmetry fixes.
> > > > >
>
Bootstrapped and tested on x86_64-unknown-linux-gnu, applied.
Richard.
2015-12-17 Richard Biener
PR tree-optimization/68951
* tree-vect-data-refs.c (vect_peeling_hash_get_lowest_cost):
Ignore strided non-group accesses.
* gcc.dg/torture/pr68951.c: New testcas
On 12/17/2015 02:57 PM, Richard Biener wrote:
On Thu, 17 Dec 2015, Yury Gribov wrote:
That's an interesting one. The original comparison function assumes that
operand_equal_p(a,b) is true iff compare_tree(a, b) == 0.
Unfortunately that's not true (functions are written by different authors).
T
On 12/17/2015 03:25 PM, Richard Biener wrote:
On Thu, 17 Dec 2015, Yury Gribov wrote:
On 12/17/2015 02:59 PM, Richard Biener wrote:
On Thu, 17 Dec 2015, Yury Gribov wrote:
On 12/17/2015 02:41 PM, Richard Biener wrote:
On Thu, 17 Dec 2015, Yury Gribov wrote:
Some obvious symmetry fixes.
C
On 17.12.2015 15:13, Yury Gribov wrote:
On 12/17/2015 02:58 PM, Andrey Belevantsev wrote:
Hello,
On 17.12.2015 11:58, Yury Gribov wrote:
Some obvious symmetry fixes.
Cc-ing
* Andrey (Belevantsev) for bb_top_order_comparator
Here, as Jakub mentioned, we assume that the argument addresses wil
On Thu, 17 Dec 2015, Yury Gribov wrote:
> On 12/17/2015 02:57 PM, Richard Biener wrote:
> > On Thu, 17 Dec 2015, Yury Gribov wrote:
> >
> > > That's an interesting one. The original comparison function assumes that
> > > operand_equal_p(a,b) is true iff compare_tree(a, b) == 0.
> > > Unfortunatel
On Thu, Dec 17, 2015 at 2:04 AM, Uros Bizjak wrote:
> On Thu, Dec 17, 2015 at 12:29 AM, H.J. Lu wrote:
>> Since sibcall never returns, we can only use call-clobbered register
>> as GOT base. Otherwise, callee-saved register used as GOT base won't
>> be properly restored.
>>
>> Tested on x86-64 w
On 12/17/2015 10:59 AM, Richard Biener wrote:
+extern void gt_ggc_mx (gimple *&);
+extern void gt_pch_nx (gimple *&);
+
This doesn't occur in the ChangeLog - unrelated change?
Bernd
On 12/17/2015 12:17 AM, Bernd Edlinger wrote:
this is just an idea, how to avoid use of malloc in unwind-ia64.c.
[...]
What do you think?
Not worth worrying about IMO. I think ia64 is dead and best left to rest
in maintenance mode.
Bernd
On Thu, 17 Dec 2015, Bernd Schmidt wrote:
> On 12/17/2015 10:59 AM, Richard Biener wrote:
> >
> > +extern void gt_ggc_mx (gimple *&);
> > +extern void gt_pch_nx (gimple *&);
> > +
>
> This doesn't occur in the ChangeLog - unrelated change?
Not unrelated, it's required to make gtype-desc.c compi
On Thu, 17 Dec 2015, Paolo Carlini wrote:
Hi,
On 16/12/2015 23:10, Patrick Palka wrote:
gcc/cp/ChangeLog:
PR c++/59878
* typeck.c (convert_for_initialization): Don't perform an early
decaying conversion if converting to a class type.
gcc/testsuite/ChangeLog:
PR c++/59878
On 17/12/15 09:31, Claudiu Zissulescu wrote:
Please find a new patch that refurbishes and extends the builtin function
support for ARC. I also added a number of builtins for ARCv2 architecture, and
a number of tests.
Ok to commit?
gcc/
2015-12-14 Claudiu Zissulescu
...
(VUNSPEC_DE
James Greenhalgh wrote:
> On Wed, Dec 16, 2015 at 01:05:21PM +, Wilco Dijkstra wrote:
> > James Greenhalgh wrote:
> > > On Tue, Dec 15, 2015 at 10:54:49AM +, Wilco Dijkstra wrote:
> > > > ping
> > > >
> > > > > -Original Message-
> > > > > From: Wilco Dijkstra [mailto:wilco.dijks...
On Thu, Dec 17, 2015 at 2:00 PM, H.J. Lu wrote:
> On Thu, Dec 17, 2015 at 2:04 AM, Uros Bizjak wrote:
>> On Thu, Dec 17, 2015 at 12:29 AM, H.J. Lu wrote:
>>> Since sibcall never returns, we can only use call-clobbered register
>>> as GOT base. Otherwise, callee-saved register used as GOT base w
On 12/17/2015 06:17 AM, Bernd Schmidt wrote:
On 12/17/2015 12:17 AM, Bernd Edlinger wrote:
this is just an idea, how to avoid use of malloc in unwind-ia64.c.
[...]
What do you think?
Not worth worrying about IMO. I think ia64 is dead and best left to rest
in maintenance mode.
Agreed. And in
On 12/16/2015 10:30 PM, Jason Merrill wrote:
OK with those changes.
All changes done, and all patches pushed. Thank you very much!!
--
Pierre-Marie de Rodat
These two tests require label values, annotated thusly.
nathan
2015-12-17 Nathan Sidwell
* c-c++-common/Wunused-var-13.c: Requires label values.
* gcc.dg/torture/pr46216.c: Likewise.
Index: c-c++-common/Wunused-var-13.c
===
-
This fixes PR68946.
Bootstrapped on x86_64-unknown-linux-gnu, testing in progress.
Richard.
2015-12-17 Richard Biener
PR tree-optimization/68946
* tree-vect-slp.c (vect_slp_analyze_node_operations): Push
SLP def type to stmt operands one stmt at a time.
* gc
Hi Kyrill,
On Tue, Dec 15, 2015 at 05:07:41PM +, Kyrill Tkachov wrote:
> As part of the war on conditional compilation here's an #if check on
> WORD_REGISTER_OPERATIONS that
> seems to have been missed out.
>
> Bootstrapped and tested on arm, aarch64, x86_64.
>
> Is it still ok to commit th
On Thu, Dec 17, 2015 at 01:22:06PM +0100, Alessandro Fanfarillo wrote:
>
> I've noticed that this patch has been applied only on trunk and not on
> the gcc-5-branch. Is it a problem to include EVENTS in gcc-5?
>
No problem. When I applied the EVENTS patch to trunk,
the 5.3 release was being pre
Hi,
On Thu, Dec 17, 2015 at 12:02:11PM +0300, Yury Gribov wrote:
> Another intransitive comparison in reload_pseudo_compare_func. Buggy
> scenario:
> 1) A and B are ints of equal presion so we return 0
> 2) C is REAL and thus can compare differently to A and B
>
> Cc-ing Martin who's the original
This reorders the hardregs to be a contiguous block, and names them somewhat
more conventionally. (I had considered %sp, %fp etc, but went with the longer
names).
nathan
2015-12-17 Nathan Sidwell
* config/nvptx/nvptx.h (NVPTX_RETURN_REGNUM, FRAME_POINTER_REGNUM,
ARG_POINTER_REGNUM, STA
On 17/12/15 10:46, Richard Biener wrote:
On Thu, 17 Dec 2015, Alan Lawrence wrote:
On 16/12/15 15:01, Richard Biener wrote:
The following patch adds a heuristic to prefer store/load-lanes
over SLP when vectorizing. Compared to the variant attached to
the PR I made the STMT_VINFO_STRIDED_P be
On Thu, Dec 17, 2015 at 03:36:18PM +0100, Kamil Rytarowski wrote:
> Hi,
>
> I talked with devs and it will be better to just keep it removed and focus on
> native NetBSD with NetBSD userland.
>
> Actually nobody seems to be interested in the Debian/NetBSD distribution.
that's what I thought fro
On Tue, Dec 15, 2015 at 03:25:18PM -0700, Jeff Law wrote:
> On 12/15/2015 03:02 PM, Trevor Saunders wrote:
> >>
> >>Can you mark interix as obsolete? It hasn't even built for a long time.
> >
> > Sure, I can do that if you want, I just wasn't sure before you wanted
> > to.
> Please do. I know w
Hi all,
In this PR I'm trying to increase the use of the aarch64 instruction TST that
performs a
bitwise AND with a bitmask and compares the result with zero.
GCC has many ways of representing these operations in RTL. Depending on the
mask, the target
and the context it might be an AND-immediat
Hi all,
The documentation on RTL canonical forms in md.texi says:
"Equality comparisons of a group of bits (usually a single bit) with zero
will be written using @code{zero_extract} rather than the equivalent
@code{and} or @code{sign_extract} operations. "
However, this is not always followed
On Thu, Dec 17, 2015 at 5:42 AM, Uros Bizjak wrote:
> On Thu, Dec 17, 2015 at 2:00 PM, H.J. Lu wrote:
>> On Thu, Dec 17, 2015 at 2:04 AM, Uros Bizjak wrote:
>>> On Thu, Dec 17, 2015 at 12:29 AM, H.J. Lu wrote:
Since sibcall never returns, we can only use call-clobbered register
as GOT
On 12/17/2015 04:36 PM, Kyrill Tkachov wrote:
The documentation on RTL canonical forms in md.texi says:
"Equality comparisons of a group of bits (usually a single bit) with zero
will be written using @code{zero_extract} rather than the equivalent
@code{and} or @code{sign_extract} operations.
On 17/12/15 15:58, Bernd Schmidt wrote:
On 12/17/2015 04:36 PM, Kyrill Tkachov wrote:
The documentation on RTL canonical forms in md.texi says:
"Equality comparisons of a group of bits (usually a single bit) with zero
will be written using @code{zero_extract} rather than the equivalent
@co
On 12/17/2015 05:10 PM, Kyrill Tkachov wrote:
Well, this patch still produces the QImode comparison if the target has
a QImode comparison
(the have_insn_for check in the simplify_comparison hunk).
Ok, I didn't look that closely because I had doubts about the approach.
This kind of check also g
On Thu, Dec 17, 2015 at 7:50 AM, H.J. Lu wrote:
> On Thu, Dec 17, 2015 at 5:42 AM, Uros Bizjak wrote:
>> On Thu, Dec 17, 2015 at 2:00 PM, H.J. Lu wrote:
>>> On Thu, Dec 17, 2015 at 2:04 AM, Uros Bizjak wrote:
On Thu, Dec 17, 2015 at 12:29 AM, H.J. Lu wrote:
> Since sibcall never retur
Great! Thanks.
2015-12-17 15:57 GMT+01:00 Steve Kargl :
> On Thu, Dec 17, 2015 at 01:22:06PM +0100, Alessandro Fanfarillo wrote:
>>
>> I've noticed that this patch has been applied only on trunk and not on
>> the gcc-5-branch. Is it a problem to include EVENTS in gcc-5?
>>
>
> No problem. When I
On 17/12/15 16:12, Bernd Schmidt wrote:
On 12/17/2015 05:10 PM, Kyrill Tkachov wrote:
Well, this patch still produces the QImode comparison if the target has
a QImode comparison
(the have_insn_for check in the simplify_comparison hunk).
Ok, I didn't look that closely because I had doubts abou
On 14/12/15 15:14, Richard Biener wrote:
The following fixes PR68852 - so I finally needed to sit down and
fix the "build-from-scalars" hack in the SLP vectorizer by pretending
we'd have a sane vectorizer IL. Basically I now mark the SLP node
with a proper vect_def_type but I have to push that
When I changed build_typeid to take the address of a polymorphic operand
rather than using the lvalue directly, I forgot the parallel change from
stabilize_reference to save_expr.
Tested x86_64-pc-linux-gnu, applying to trunk and 5.
commit 5361caf55040d2a15b5ebb5ff0fc1e3e605dba9c
Author: Jason
On 12/17/2015 08:58 AM, Bernd Schmidt wrote:
On 12/17/2015 04:36 PM, Kyrill Tkachov wrote:
The documentation on RTL canonical forms in md.texi says:
"Equality comparisons of a group of bits (usually a single bit) with zero
will be written using @code{zero_extract} rather than the equivalent
Just committed.revision 231774
Andris
Index: MAINTAINERS
===
--- MAINTAINERS (revision 231774)
+++ MAINTAINERS (working copy)
@@ -525,6 +525,7 @@
Patrick Palka
Seongbae Park
Devang Patel
+Andris Pavenis
Fernando Pereira
Ka
Since Pmode is 64-bit with -maddress-mode=long for x32, indirect call
via GOT slot doesn't need zero_extend. This patch limits *call_got_x32
and *call_value_got_x32 patterns to 32-bit Pmode, adds *call_got_x32_long
and *call_value_got_x32_long for 64-bit Pmode.
OK for trunk if there is no regress
In my rework of decl_constant_value and kin, I enabled its use in more
places, which revealed a problem: when it is allowing non-constexpr
aggregate initializers, we need to double-check that we aren't returning
something that had initializers stripped out in split_nonconstant_init.
Tested x86
On 12/17/2015 08:58 AM, Bernd Schmidt wrote:
I suspect that this is an oversight in the documentation, and if given
two choices the simpler form is intended to be the canonical one.
The other BZ I was looking at in this space was 15596. It's PPC, but
shows a generic weakness in how we identify
2015-12-16 10:08 GMT+03:00 Senthil Kumar Selvaraj
:
> Hi,
>
> When analyzing code size regressions for AVR for top-of-trunk, I
> found a few cases where aggresive inlining (by the middle-end)
> of functions containing calls to memcpy was bloating up the code.
>
> Turns out that the AVR back
On 12/17/2015 09:26 AM, Kyrill Tkachov wrote:
One could argue that if the target has (or advertises having) a native
QImode register comparison then it's objectively a simplification to
transform a comparison in a wider mode
to a comparison in the shorter mode.
Generally true.
The most commonly
Hi Jeff,
On 17/12/15 16:59, Jeff Law wrote:
On 12/17/2015 09:26 AM, Kyrill Tkachov wrote:
One could argue that if the target has (or advertises having) a native
QImode register comparison then it's objectively a simplification to
transform a comparison in a wider mode
to a comparison in the sho
On Thu, Dec 17, 2015 at 03:36:40PM +, Kyrill Tkachov wrote:
> 2015-12-17 Kyrylo Tkachov
>
> PR rtl-optimization/68796
> * config/aarch64/aarch64.md (*and3nr_compare0_zextract):
> New pattern.
> * config/aarch64/aarch64.c (aarch64_select_cc_mode): Handle
> ZERO_EXTRACT co
1 - 100 of 150 matches
Mail list logo
