Andi Kleen writes:
> On Sun, Nov 15, 2015 at 11:09:18PM +0100, Andreas Schwab wrote:
>> Andi Kleen writes:
>>
>> > Fix the obivous typos. To to commit?
>>
>> They are not typos.
>
> Ok. What do you suggest to fix the error then?
Someone will need to fix the regression introduced by the C++ de
On 16.11.2015 03:00, David Edelsohn wrote:
>[..]
> Ten days and still waiting for a response on libtool-patches.
>
> - David
>
Drop a hint to libt...@gnu.org?
--
VH
signature.asc
Description: OpenPGP digital signature
On Fri, 13 Nov 2015, Alan Lawrence wrote:
> On 10/11/15 09:34, Richard Biener wrote:
> >
> > The following fixes PR56118 by adjusting the cost model handling of
> > basic-block vectorization to favor the vectorized version in case
> > estimated cost is the same as the estimated cost of the scalar
This adjusts mentioned testcase to make it more reliably pass.
Tested on x86_64-unknown-linux-gnu.
Richard.
2015-11-16 Richard Biener
* gcc.dg/vect/bb-slp-32.c: Adjust testcase.
Index: gcc/testsuite/gcc.dg/vect/bb-slp-32.c
===
On Sat, 14 Nov 2015, Senthil Kumar Selvaraj wrote:
> On Sat, Nov 14, 2015 at 09:57:40AM +0100, Richard Biener wrote:
> > On November 14, 2015 9:49:28 AM GMT+01:00, Senthil Kumar Selvaraj
> > wrote:
> > >On Sat, Nov 14, 2015 at 09:13:41AM +0100, Marc Glisse wrote:
> > >> On Sat, 14 Nov 2015, Sent
Hi Jim,
On 13/11/15 17:53, Jim Wilson wrote:
Revised patch with the also missing xgene1 part added.
Jim
aprofile.patch
2015-11-13 Jim Wilson
* gcc/config/arm/t-aprofile (MULTILIB_MATCHES): Add lines for exynos-m1
and qdf24xx and xgene1 to match -march=armv8-a.
This is ok.
> No RISC architecture can store directly to MEM, so the expected RTL in
> g++.dg/init/vbase1.C is wrong. I am adding XFAIL for PowerPC. This
> probably should be disabled for ARM and other RISC architectures.
Some of them can store 0 directly to MEM though, for example SPARC.
--
Eric Botcazou
On Fri, Nov 13, 2015 at 11:40:56AM +0100, Richard Biener wrote:
> On Fri, Nov 13, 2015 at 11:13 AM, James Greenhalgh
> wrote:
> >
> > Hi,
> >
> > With all the work that has recently gone in to ifcvt, I thought I'd revisit
> > the branch cost settings for Cortex-A57. After a run of experiments [1],
> Since r230164, in PR68330 combine ends up with a sign_extend of an
> lshiftrt by some constant, and it does not know to morph that into a
> zero_extract (the extend will always extend with zeroes). I think
> it is best to let simplify-rtx always replace such a sign_extend by
> a zero_extend, aft
>> On Sun, Nov 15, 2015 at 11:09:18PM +0100, Andreas Schwab wrote:
>>> Andi Kleen writes:
>>>
>>> > Fix the obivous typos. To to commit?
>>>
>>> They are not typos.
>>
>> Ok. What do you suggest to fix the error then?
>Someone will need to fix the regression introduced by the C++ delayed
>folding.
On Fri, Nov 13, 2015 at 07:40:27PM +0100, Martin Jambor wrote:
> the patch below is is an untested trunk-only implementation of device
> specific GOMP_target_ext arguments, which was proposed to me by Jakub
> today on IRC. I'm sending this patch to make sure I understood the
> details well. Never
On 15/11/15 16:38 -0500, Jennifer Yao wrote:
I just finished running the testsuite on x86_64-pc-cygwin for
Jonathan's latest patch and compared the results against an older
(about two months old) run, and so far I'm not seeing any regressions.
Granted, this is strictly preliminary; I'm currently
On Sun, Nov 15, 2015 at 12:14 PM, Kumar, Venkataramanan
wrote:
> Hi Richard and Bernhard.
>
>> -Original Message-
>> From: Richard Biener [mailto:richard.guent...@gmail.com]
>> Sent: Tuesday, November 10, 2015 5:33 PM
>> To: Kumar, Venkataramanan
>> Cc: Andrew Pinski; gcc-patches@gcc.gnu.
This patch adds support for atomic memory built-in for ARCHS and ARC700. Tested
with dg.exp.
OK to apply?
Thanks,
Claudiu
ChangeLogs:
gcc/
2015-11-12 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_expand_atomic_op): Prototype.
(arc_split_compare_and_swap): Likewise.
On 13/11/15 10:13, James Greenhalgh wrote:
>
> Hi,
>
> With all the work that has recently gone in to ifcvt, I thought I'd revisit
> the branch cost settings for Cortex-A57. After a run of experiments [1],
> I found {1, 3} to be the sweet spot, giving a small set of performance
> improvements acr
On 15/11/15 22:12 +0100, François Dumont wrote:
Here is a last version I think.
I completed the debug light mode by adding some check on iterator
ranges.
Even if check are light I made some changes to make sure that
internally vector is not using methods instrumented with those checks.
Th
Hi,
This patch changes the target support mechanism to make it recognize
any ARM 'M' profile as a non-neon supporting target. The current check
only tests for armv6 architectures and earlier, and does not account for
armv7-m.
This is correct because there is no 'M' profile that supports
Ville Voutilainen writes:
>
> The proposed patch makes no sense. The assignment is intentional,
> the relevant flags of the element type are reflected onto the array type.
> Doing a comparison there instead of assignment will not have the
> desired effect.
Ok I changed it to an assignment.
> May
On Sun, Nov 15, 2015 at 9:21 AM, Andris Pavenis wrote:
> This fixes use of pointers different unsigned integer types as function
> parameter.
> Function prototype is (see gcc/tree-streamer.h):
>
> bool streamer_tree_cache_lookup (struct streamer_tree_cache_d *, tree,
> unsigned *)
> I'm just going to use --disable-werror now, as apparently everybody else
> does.
I personally don't and bootstrap works fine probably because the bug is fixed.
Are you sure that you are bootstrapping the compiler and not just building it?
-Werror is supposed to be disabled during stage #1 of a b
In r229405 I removed a call to redirect_edge_var_map_destroy from
delete_tree_ssa which I thought cannot be necessary because that
map isn't GCed and thus stale data in it should have caused quite
some havoc otherwise. Turns out I was wrong ;) We were lucky
instead. The following patch amends t
Eric Botcazou writes:
> I personally don't and bootstrap works fine probably because the bug is fixed.
No, the bug still exists. Try --enable-checking=release.
Andreas.
--
Andreas Schwab, sch...@linux-m68k.org
GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now
On 11/11/15 11:55, Richard Biener wrote:
On Mon, 9 Nov 2015, Tom de Vries wrote:
On 09/11/15 16:35, Tom de Vries wrote:
Hi,
this patch series for stage1 trunk adds support to:
- parallelize oacc kernels regions using parloops, and
- map the loops onto the oacc gang dimension.
The patch serie
On 11/11/15 11:55, Richard Biener wrote:
On Mon, 9 Nov 2015, Tom de Vries wrote:
On 09/11/15 16:35, Tom de Vries wrote:
Hi,
this patch series for stage1 trunk adds support to:
- parallelize oacc kernels regions using parloops, and
- map the loops onto the oacc gang dimension.
The patch serie
On 13/11/15 10:34, Richard Biener wrote:
On Thu, Nov 12, 2015 at 4:07 PM, Andre Vieira
wrote:
Hi,
This patch changes this testcase to make sure LTO will not optimize away
the assignment of the local array to a global variable which was introduced
to make sure stack space was made available
> No, the bug still exists. Try --enable-checking=release.
Ah, OK, so tree checking somehow works around it I presume.
--
Eric Botcazou
> Bootstrapped and tested on x86_64-linux. Ok?
OK once the 2/2 patch is also approved.
--
Eric Botcazou
On 11/11/15 12:02, Richard Biener wrote:
On Mon, 9 Nov 2015, Tom de Vries wrote:
On 09/11/15 16:35, Tom de Vries wrote:
Hi,
this patch series for stage1 trunk adds support to:
- parallelize oacc kernels regions using parloops, and
- map the loops onto the oacc gang dimension.
The patch serie
On 09/11/15 20:52, Tom de Vries wrote:
On 09/11/15 16:35, Tom de Vries wrote:
Hi,
this patch series for stage1 trunk adds support to:
- parallelize oacc kernels regions using parloops, and
- map the loops onto the oacc gang dimension.
The patch series contains these patches:
1Insert
On 11/11/15 12:05, Richard Biener wrote:
On Mon, 9 Nov 2015, Tom de Vries wrote:
On 09/11/15 16:35, Tom de Vries wrote:
Hi,
this patch series for stage1 trunk adds support to:
- parallelize oacc kernels regions using parloops, and
- map the loops onto the oacc gang dimension.
The patch serie
On 11/16/2015 12:54 PM, Eric Botcazou wrote:
Bootstrapped and tested on x86_64-linux. Ok?
OK once the 2/2 patch is also approved.
Thank you. The 2/2 has a small regrename piece to add target_data
fields, are you OK with that as well? I'm assuming Uros will take a look
at the rest.
Bernd
On Mon, Nov 16, 2015 at 10:49:11AM +, Andre Vieira wrote:
> Hi,
>
> This patch changes the target support mechanism to make it
> recognize any ARM 'M' profile as a non-neon supporting target. The
> current check only tests for armv6 architectures and earlier, and
> does not account for armv7
On 11/15/2015 11:55 AM, Tom de Vries wrote:
[ was: Re: [PATCH] Remove first_pass_instance from pass_vrp ]
This patch series removes first_pass_instance.
1Remove first_pass_instance from pass_vrp
2Remove first_pass_instance from pass_reassoc
3Remove first_pass_insta
> Thank you. The 2/2 has a small regrename piece to add target_data
> fields, are you OK with that as well?
Sure.
--
Eric Botcazou
On 03/11/15 14:27, Alan Lawrence wrote:
This migrates the various reduction optabs in sse.md to use the reduce-to-scalar
form. I took the straightforward approach (equivalent to the migration code in
expr.c/optabs.c) of generating a vector temporary, using the existing code to
reduce to that, and
On Mon, 16 Nov 2015, Tom de Vries wrote:
> On 11/11/15 11:55, Richard Biener wrote:
> > On Mon, 9 Nov 2015, Tom de Vries wrote:
> >
> > > On 09/11/15 16:35, Tom de Vries wrote:
> > > > Hi,
> > > >
> > > > this patch series for stage1 trunk adds support to:
> > > > - parallelize oacc kernels regi
The scan-assembler vclz2s 34 test in here has been failing since r230091:
* tree-vect-slp.c (vect_bb_vectorization_profitable_p): Make equal
cost favor vectorized version.
which transforms a load of piecewise array assignments (in tree) into
2-element-vector writes to MEMs, an
On Mon, 16 Nov 2015, Tom de Vries wrote:
> On 11/11/15 12:02, Richard Biener wrote:
> > On Mon, 9 Nov 2015, Tom de Vries wrote:
> >
> > > On 09/11/15 16:35, Tom de Vries wrote:
> > > > Hi,
> > > >
> > > > this patch series for stage1 trunk adds support to:
> > > > - parallelize oacc kernels regi
On 11/15/2015 11:14 PM, Dhole wrote:
gcc/c-family/ChangeLog:
2015-10-10 Eduard Sanou
I can't find a previous change from you in the sources, so the first
question would be whether you've gone through the copyright assignment
process.
Bernd
On 16/11/15 13:09, Bernd Schmidt wrote:
On 11/15/2015 11:55 AM, Tom de Vries wrote:
[ was: Re: [PATCH] Remove first_pass_instance from pass_vrp ]
This patch series removes first_pass_instance.
1Remove first_pass_instance from pass_vrp
2Remove first_pass_instance from pass_r
Hello Alan,
On 16 Nov 12:23, Alan Lawrence wrote:
> On 03/11/15 14:27, Alan Lawrence wrote:
> >This migrates the various reduction optabs in sse.md to use the
> >reduce-to-scalar
> >form. I took the straightforward approach (equivalent to the migration code
> >in
> >expr.c/optabs.c) of generating
On 16/11/15 12:07, James Greenhalgh wrote:
On Mon, Nov 16, 2015 at 10:49:11AM +, Andre Vieira wrote:
Hi,
This patch changes the target support mechanism to make it
recognize any ARM 'M' profile as a non-neon supporting target. The
current check only tests for armv6 architectures and earl
Hi all,
This RTL checking ICE occurs when processing an rtx_insn* in
aarch64_madd_needs_nop that apparently
holds JUMP_TABLE_DATA. This shouldn't be passed to recog. So instead reject it
with the INSN_P check.
Such rtx_insns are not relevant to the code in aarch64_madd_needs_nop anyway.
Bootst
On Mon, Nov 16, 2015 at 4:15 AM, Eric Botcazou wrote:
>> No RISC architecture can store directly to MEM, so the expected RTL in
>> g++.dg/init/vbase1.C is wrong. I am adding XFAIL for PowerPC. This
>> probably should be disabled for ARM and other RISC architectures.
>
> Some of them can store 0
On Mon, Nov 16, 2015 at 12:43 PM, Andre Vieira
wrote:
> On 13/11/15 10:34, Richard Biener wrote:
>>
>> On Thu, Nov 12, 2015 at 4:07 PM, Andre Vieira
>> wrote:
>>>
>>> Hi,
>>>
>>>This patch changes this testcase to make sure LTO will not optimize
>>> away
>>> the assignment of the local array
On 11/13/2015 11:30 PM, Marc Glisse wrote:
+__asm__("posix_memalign");
Can't say I like the __asm__ after the #if/#else/#endif block.
It might also cause trouble if some systems like to prepend an
underscore, maybe?
Yeah, that's one of the things I had in mind when I suggested moving
this
On Thu, Nov 12, 2015 at 7:35 PM, Alan Lawrence wrote:
> On 06/11/15 16:29, Richard Biener wrote:
2) You should be able to use fold_ctor_reference directly (in place
>>> of
all your code
in case offset and size are readily available - don't remember
>>> exactly how
complete scal
On Fri, Nov 13, 2015 at 12:27 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Tue, Nov 10, 2015 at 1:09 AM, Bernd Schmidt wrote:
>>> On 11/07/2015 01:46 PM, Richard Sandiford wrote:
@@ -3814,8 +3817,8 @@ extract_range_basic (value_range *vr, gimple *stmt)
bre
On Fri, Nov 13, 2015 at 1:27 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Mon, Nov 9, 2015 at 5:25 PM, Richard Sandiford
>> wrote:
>>> This patch replaces the fndecl argument to builtin_vectorized_function
>>> with a combined_fn and gets the vectoriser to call it for internal
>>>
On Fri, Nov 13, 2015 at 2:12 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Mon, Nov 9, 2015 at 10:03 PM, Michael Matz wrote:
>>> Hi,
>>>
>>> On Mon, 9 Nov 2015, Richard Sandiford wrote:
>>>
+static bool
+can_use_internal_fn (gcall *call)
+{
+ /* Only replace ca
Hi David,
On 14/11/15 00:33, David Edelsohn wrote:
No RISC architecture can store directly to MEM, so the expected RTL in
g++.dg/init/vbase1.C is wrong. I am adding XFAIL for PowerPC. This
probably should be disabled for ARM and other RISC architectures.
I observed the same problem in arm.
Hi all,
In this PR we encounter a wrong-code bug on x86_64. It started with an RTL
if-conversion patch of mine
which I believe exposed a latent issue in the ree (redundant extension
elimination) pass.
The different if-conversion behaviour enabled a new cse opportunity
which then produced the RT
On 16/11/15 13:33, Richard Biener wrote:
On Mon, Nov 16, 2015 at 12:43 PM, Andre Vieira
wrote:
On 13/11/15 10:34, Richard Biener wrote:
On Thu, Nov 12, 2015 at 4:07 PM, Andre Vieira
wrote:
Hi,
This patch changes this testcase to make sure LTO will not optimize
away
the assignment of t
Hi,
The attached patch fixes PR 68277.
Tested by Kaz on trunk on sh4-linux. I've also done a sanity check on
GCC 5 branch with "make all" on sh-elf.
Committed to trunk as r230425 and to GCC 5 branch as r230426.
Cheers,
Oleg
gcc/ChangeLog:
PR target/68277
* config/sh/sh.md (adds
On Mon, Nov 16, 2015 at 3:08 PM, Andre Vieira
wrote:
> On 16/11/15 13:33, Richard Biener wrote:
>>
>> On Mon, Nov 16, 2015 at 12:43 PM, Andre Vieira
>> wrote:
>>>
>>> On 13/11/15 10:34, Richard Biener wrote:
On Thu, Nov 12, 2015 at 4:07 PM, Andre Vieira
wrote:
>
>
>>>
Hi,
This patch adds support to the ARM back-end for the Cortex-A35
processor, as recently announced by ARM. The ARM Cortex-A35 provides
full support for the ARMv8-A architecture, including the CRC extension,
with optional Advanced-SIMD and Floating-Point support. We therefore set
feature flags fo
On 13 November 2015 at 17:18, Alan Lawrence wrote:
> On 10/11/15 12:51, Richard Biener wrote:
>>>
>>> Just noticing this... if we have a vectorization factor of 4 and matches
>>> is 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 then this will split into 1, 1, 1, 1
>>> and
>>> 1, 1, 0, 0, 0, ... where we kn
On 11/16/2015 02:05 PM, Bernd Schmidt wrote:
> On 11/15/2015 11:14 PM, Dhole wrote:
>> gcc/c-family/ChangeLog:
>>
>> 2015-10-10 Eduard Sanou
>
> I can't find a previous change from you in the sources, so the first
> question would be whether you've gone through the copyright assignment
> process.
Hi,
This patch adds support to the AArch64 back-end for the Cortex-A35
processor, as recently announced by ARM. The ARM Cortex-A35 provides
full support for the ARMv8-A architecture, including the CRC extension,
with optional Advanced-SIMD and Floating-Point support. We therefore set
feature flag
On Sun, 2015-11-15 at 15:39 -0500, Rich Felker wrote:
> > This is basically the same as above ... it's not possible to
> > conditionally construct/modify pattern descriptions in the .md.
> > However, it's possible to modify the CALL_INSN_FUNCTION_USAGE
> > field of
> > call insns -- for some exa
I made a copy&paste error in the prev rev.
Committed as obvious.
Richard.
2015-11-16 Richard Biener
* tree-vect-data-refs.c (vect_verify_datarefs_alignment): Fix
bogus copying from verify_data_ref_alignment and use continue
instead of return.
Index: gcc/tree-vect-da
Backported r227407 to gcc-5-branch following approval on IRC. The
patch applied without conflicts.
2015-11-16 Charles Baylis
Backport from mainline r227407
PR ipa/67280
* cgraphunit.c (cgraph_node::create_wrapper): Set can_throw_external
in new callgraph edge.
This follows from the discussion here:
https://gcc.gnu.org/ml/gcc/2015-10/msg00082.html .
OK for trunk?
--Alan
gcc/ChangeLog:
doc/install.texi: Add note against GNAT 4.8 on ARM targets.
---
gcc/doc/install.texi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/doc/install.texi
On 2015.08.31 at 11:31 +0200, Markus Trippelsdorf wrote:
> On 2015.08.24 at 13:44 +0200, Markus Trippelsdorf wrote:
another ping.
> ping
>
> > decl_mangling_context() in mangle.c returns a NULL_TREE in case of
> > template type parameters. write_template_prefix() needs to handle this
> > situati
I just happened to stumble on this problem with another port.
The volatile & test solution doesn't work, though.
What does work, however, is:
__asm__ ("" : : "" (dummy));
Hi!
On Mon, Oct 26, 2015 at 20:49:40 +0100, Jakub Jelinek wrote:
> On Mon, Oct 26, 2015 at 10:39:04PM +0300, Ilya Verbin wrote:
> > > Without declare target link or to, you can't use the global variables
> > > in orphaned accelerated routines (unless you e.g. take the address of the
> > > mapped v
On 16/11/15 15:34, Joern Wolfgang Rennecke wrote:
I just happened to stumble on this problem with another port.
The volatile & test solution doesn't work, though.
What does work, however, is:
__asm__ ("" : : "" (dummy));
I can confirm that Joern's solution works for me too.
Hi, everyone.
While it often (usually?) isn't an issue, passing a signed char to ctype
functions is undefined. Here's the CERT entry:
https://www.securecoding.cert.org/confluence/x/fAs
This means that we need to cast chars to unsigned char before passing
them to one of these functions.
Hi,
On Thu, 12 Nov 2015, Jeff Law wrote:
> > this new pass implements loop iteration space splitting for loops that
> > contain a conditional that's always true for one part of the iteration
> > space and false for the other, i.e. such situations:
> FWIW, Ajit suggested the same transformation ea
Hi,
On Mon, 16 Nov 2015, Richard Biener wrote:
> >> Which would leave us with a lowering stage early in the main
> >> optimization pipeline - I think fold_builtins pass is way too late
> >> but any "folding" pass will do (like forwprop or backprop where the
> >> latter might be better because
On 11/16/2015 01:12 PM, Richard Biener wrote:
On Sun, Nov 15, 2015 at 9:21 AM, Andris Pavenis wrote:
This fixes use of pointers different unsigned integer types as function
parameter.
Function prototype is (see gcc/tree-streamer.h):
bool streamer_tree_cache_lookup (struct streamer_tree_cache_d
Hello,
The command line options for target selection allow ARMv8.1 extensions
to be individually enabled/disabled. They also allow the extensions to
be enabled with -march=armv8-a. This doesn't reflect the ARMv8.1
architecture which requires all extensions to be enabled and doesn't make
them avai
On 16/11/15 13:42, Bernd Schmidt wrote:
On 11/13/2015 11:30 PM, Marc Glisse wrote:
+__asm__("posix_memalign");
Can't say I like the __asm__ after the #if/#else/#endif block.
It might also cause trouble if some systems like to prepend an
underscore, maybe?
Yeah, that's one of the things I h
On Mon, Nov 16, 2015 at 8:31 AM, Matthew Wahab
wrote:
> Hello,
>
> The command line options for target selection allow ARMv8.1 extensions
> to be individually enabled/disabled. They also allow the extensions to
> be enabled with -march=armv8-a. This doesn't reflect the ARMv8.1
> architecture which
On 16/11/15 14:42, James Greenhalgh wrote:
Hi,
This patch adds support to the ARM back-end for the Cortex-A35
processor, as recently announced by ARM. The ARM Cortex-A35 provides
full support for the ARMv8-A architecture, including the CRC extension,
with optional Advanced-SIMD and Floating-Poi
On Tue, Sep 08, 2015 at 22:41:17 +0300, Ilya Verbin wrote:
> This patch supports unloading of target images from the device.
> Unfortunately __offload_unregister_image requires the whole descriptor for
> unloading, which must contain target code inside, for this reason the plugin
> keeps descriptor
-Original Message-
From: Jeff Law [mailto:l...@redhat.com]
Sent: Friday, November 13, 2015 11:44 AM
To: Ajit Kumar Agarwal; GCC Patches
Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala
Subject: Re: [RFC, Patch]: Optimized changes in the register used inside lo
While waiting for a build to finish I figured I might as well do this.
Bootstrapped/regtested on x86_64-linux, applying to trunk.
2015-11-16 Marek Polacek
* c-ada-spec.c (dump_ada_template): Use RECORD_OR_UNION_TYPE_P.
* c-common.c (c_common_get_alias_set): Likewise.
(
Sorry I missed out some of the points in earlier mail which is given below.
-Original Message-
From: Ajit Kumar Agarwal
Sent: Monday, November 16, 2015 11:07 PM
To: 'Jeff Law'; GCC Patches
Cc: Vinod Kathail; Shail Aditya Gupta; Vidhumouli Hunsigida; Nagaraju Mekala
Subject: RE: [RFC, Pat
So Jeff and I just had a chat, and we came up with some thoughts about
how to proceed. I think we both agree that it would be good to have a
special testing backend, along with frontends designed to be able to
read in gimple or rtl that can be operated on. That's more of a
long-term thing.
Fo
On Fri, Nov 13, 2015 at 9:47 PM, Bernd Schmidt wrote:
> This adds a new -mmitigate-rop option to the i386 port. The idea is to
> mitigate against certain forms of attack called "return oriented
> programming" that some of our security folks are concerned about. The basic
> idea is that the stack g
On 11/16/2015 03:07 PM, Kyrill Tkachov wrote:
I've explained in the comments in the patch what's going on but the
short version is trying to change the destination of a defining insn
that feeds into an extend insn is not valid if the defining insn
doesn't feed directly into the extend insn. In t
On 09/11/15 12:55, Richard Biener wrote:
Currently BB vectorization computes all dependences inside a BB
region and fails all vectorization if it cannot handle some of them.
This is obviously not needed - BB vectorization can restrict the
dependence tests to those that are needed to apply the l
On Mon, 2015-11-16 at 19:17 +0100, Bernd Schmidt wrote:
> So Jeff and I just had a chat, and we came up with some thoughts about
> how to proceed. I think we both agree that it would be good to have a
> special testing backend, along with frontends designed to be able to
> read in gimple or rtl
On 11/10/2015 01:10 PM, Jonathan Wakely wrote:
> On 06/11/15 09:59 +, Pedro Alves wrote:
>> On 11/06/2015 01:56 AM, Jonathan Wakely wrote:
>>> On 5 November 2015 at 23:31, Daniel Gutson
>>
The issue is, as I understand it, to do the actual work of operator
new, i.e. allocate memory. I
This patch ought to fix a regression introduced by the C++ delayed folding
merge. What happens here for this testcase is that in c_add_case_label we
convert "0" to NOP_EXPR: "(const A) 0" in convert_and_check. We pass this
to check_case_bounds which only expects INTEGER_CSTs. Since we can't use
> More comments inline.
Revised version attached, which addresses all your comments and in particular
removes the
+#if PROBE_INTERVAL > 4096
+#error Cannot use indexed addressing mode for stack probing
+#endif
compile-time assertion. It generates the same code for PROBE_INTERVAL == 4096
as be
OK.
Jason
Hi Jeff,
(Sorry I didn't reply sooner, I was OOO.)
On 11/08/2015 11:17 PM, Jeff Law wrote:
> On 11/07/2015 07:31 AM, Pedro Alves wrote:
>> Hi Richard,
>>
>> Passerby comment below.
>>
>> On 11/07/2015 01:21 PM, Richard Sandiford wrote:
>>> -/* Lookup the identifier ID. */
>>> +/* Lookup the iden
On 11/16/2015 01:15 PM, Pedro Alves wrote:
Hi Jeff,
(Sorry I didn't reply sooner, I was OOO.)
No worries.
Boolean params are best avoided if possible, IMO. In this case,
it seems this could instead be a new wrapper function, like:
This hasn't been something we've required for GCC.I've
On Sat, 2015-11-14 at 23:32 -0500, David Malcolm wrote:
> On Sat, 2015-11-14 at 09:50 -0500, David Edelsohn wrote:
> > This patch causes numerous new testsuite failure on AIX caused by the
> > compiler crashing during compilation, e.g.
> >
> > gcc.c-torture/execute/20020206-1.c
> >
> > in GCC lib
On 11/15/2015 07:27 PM, tbsaunde+...@tbsaunde.org wrote:
From: Trevor Saunders
Some of the pa target macros rely on macros in emit-rtl.h and sdbout.c
uses some of those macros, which means that sdbout.c needs to include
emit-rtl.h.
this seems obvious, bootstrapped on x86_64-linux-gnu, and chec
Hi.
Apologies for the delay.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67440
Tested with current trunk.
2015-11-16 Doug Evans
PR libstdc++/67440
* python/libstdcxx/v6/printers.py (find_type): Handle "const" in
type name.
* testsuite/libstdc++-prettyprinter
On 11/16/2015 09:22 AM, Andris Pavenis wrote:
On 11/16/2015 01:12 PM, Richard Biener wrote:
On Sun, Nov 15, 2015 at 9:21 AM, Andris Pavenis
wrote:
This fixes use of pointers different unsigned integer types as function
parameter.
Function prototype is (see gcc/tree-streamer.h):
bool streamer_
For some of the simpler infrastructure tests such as the ones in this
patch kit (bitmap, vec or wide-int functionality testing and such), we
had the idea of putting these into every ENABLE_CHECKING compiler, and
run them after building stage1, controlled by a -fself-test flag. It's
better to det
On 16/11/15 21:04 +, Doug Evans wrote:
Hi.
Apologies for the delay.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67440
Tested with current trunk.
2015-11-16 Doug Evans
PR libstdc++/67440
* python/libstdcxx/v6/printers.py (find_type): Handle "const" in
type name.
Hi,
while playing around with inserting pass_ccp here and there in the pass
list, I put it after a pass where the loops state contained LOOP_CLOSED_SSA.
And apparently pass_ccp does not preserve loop-closed ssa.
As a consequence, during executing the pass_ccp todos,
verify_loop_closed_ssa fa
On 11/16/2015 09:50 PM, David Malcolm wrote:
The root cause is uninitialized data. Specifically, the C parser's
struct c_expr gained a "src_range" field, and it turns out there are a
few places where I wasn't initializing this when returning c_expr
instances on the stack, and in some cases the v
Hi,
pass_scev_cprop contains a bit where it replaces uses of an ssa-name
with constants. This is currently not noted in the dump-file, even with
TDF_DETAILS.
This patch adds that information in the dump-file, in this format:
...
Replacing uses of: D__lsm.10_34 with: 1
...
OK for trunk i
Jeff Law writes:
Boolean params are best avoided if possible, IMO. In this case,
it seems this could instead be a new wrapper function, like:
>>> This hasn't been something we've required for GCC.I've come across
>>> this recommendation a few times over the last several months as I
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