Re: [PATCH] SH FDPIC backend support

Oleg Endo wrote: >> So apparently the strange behavior I observed is intended. Presumably >> there is some mechanism to ensure that these functions are always >> static-linked? But I don't see it. The libgcc spec I see is: >> >> *libgcc: >> %{static|static-libgcc:-lgcc >> -lgcc_eh}%{!static:%{!st

Re: RFC: Patch to allow spill slot alignment greater than the stack alignment

On 10/02/2015 10:57 PM, Steve Ellcey wrote: I have spent some time trying to do dynamic stack alignment on MIPS and had considerable trouble. The problems are mainly due to the dwarf based stack unwinding and setjmp/longjmp usages where the code does not go through the normal function prologue a

Re: [PATCH 0/4] gimple accessor const correctness fixes

On 10/05/2015 02:25 AM, tbsaunde+...@tbsaunde.org wrote: the first patch is just some cleanup I ran into along the way, but the rest of this series fixes const correctness for all of the gimple_x_ptr () functions. I was able to just remove a couple of them, but unfortunately most ar needed for e

Re: [PATCH] Add verifier for leaked SSA names

On Fri, Oct 2, 2015 at 5:24 PM, Jeff Law wrote: > On 10/02/2015 01:37 AM, Richard Biener wrote: >> >> >> The following patch doesn't pass bootstrap & regtest. It did at some >> point though and its comment hints that fixing leaks after inlining >> was too interesting a problem to solve ;) >> >> T

Re: [PATCH] x86 interrupt attribute

On Oct 4, 2015, at 11:15 AM, H.J. Lu wrote: > Current stack alignment implementation requires at least > one, maybe two, scratch registers: So, I have some cases where I need scratch registers as well. I always save 2 registers and they go first (and restore last), so I can always use them.

Re: RFC: PATCH for front end parts of C++ transactional memory TS

Jason Merrill writes: > diff --git a/gcc/testsuite/g++.dg/tm/eh1.C b/gcc/testsuite/g++.dg/tm/eh1.C > new file mode 100644 > index 000..1561211 > --- /dev/null > +++ b/gcc/testsuite/g++.dg/tm/eh1.C > @@ -0,0 +1,10 @@ > +// A handler can involve a transaction-safety conversion. > +// { dg-do ru

[Patch, avr] Fix PR 67839 - bit addressable instructions generated for out of range addresses

Hi, As part of support for io and io_low attributes, the upper bound of the range check for low IO and IO addresses was changed from hardcoded values to hardcoded_range_end + 1 - GET_MODE_SIZE(mode). GCC passes VOID as the mode from genrecog, and GET_MODE_SIZE returns 0, resulting in th

Re: [PATCH] Improve DOM's optimization of control statements

On Fri, Oct 2, 2015 at 9:30 PM, Jeff Law wrote: > On 10/02/2015 05:15 AM, Renlin Li wrote: >> >> Hi Jeff, >> >> Your patch causes an ICE regression. >> The test case is " gcc.c-torture/compile/pr27087.c", I observed it on >> aarch64-none-elf target when compiling the test case with '-Os' flag. >>

Re: [PATCH 1/4] make build_uses store tree * instead of tree

On Mon, Oct 5, 2015 at 2:25 AM, wrote: > From: Trevor Saunders > > gcc/ChangeLog: > > 2015-10-04 Trevor Saunders > > * tree-ssa-operands.c (build_uses): store tree * instead of > tree. > (finalize_ssa_uses): Adjust. > (append_use): Likewise. > (verify_s

Re: [PATCH 3/4] remove unused gasm accessors

On Mon, Oct 5, 2015 at 2:25 AM, wrote: > From: Trevor Saunders > > gcc/ChangeLog: > > 2015-10-04 Trevor Saunders > > * gimple.h (gimple_asm_input_op_ptr): Remove. > (gimple_asm_output_op_ptr): Likewise. Ok. Thanks, Richard. > --- > gcc/gimple.h | 20 >

Re: [PATCH 2/4] remove gimple_location_ptr ()

On Mon, Oct 5, 2015 at 2:25 AM, wrote: > From: Trevor Saunders > > gcc/ChangeLog: > > 2015-10-04 Trevor Saunders > > * gimple.h (gimple_location_ptr): Remove. > * tree-vrp.c (check_all_array_refs): Adjust. Ok. Thanks, RIchard. > --- > gcc/gimple.h | 9 - > gcc/tr

Re: [PATCH 4/4] make more gimple_x_ptr accessors const correct

On Mon, Oct 5, 2015 at 2:25 AM, wrote: > From: Trevor Saunders > > gcc/ChangeLog: > > 2015-10-04 Trevor Saunders > > * gimple.h (gimple_op_ptr): Require a non const gimple *. > (gimple_assign_lhs_ptr): Likewise. > (gimple_assign_rhs1_ptr): Likewise. > (gimple_a

Re: [PATCH] x86 interrupt attribute

On Mon, Oct 5, 2015 at 1:17 AM, H.J. Lu wrote: >> Looking a bit deeper into the code, it looks that we want to realign >> the stack in the interrupt handler. Let's assume that interrupt >> handler is calling some other function that saves SSE vector regs to >> the stack. According

Re: [v3 PATCH] PR 67844

On 05/10/15 06:59 +0300, Ville Voutilainen wrote: PR 67844. * include/std/tuple (_TC::_NonNestedTuple): Eagerly reject conversions from tuple types same as the target tuple. * testsuite/20_util/tuple/67844.cc: New. OK for trunk with a copyright header on the testcase. Thanks for the

Re: C PATCH for c/65345 (file-scope _Atomic expansion with floats)

On 2 October 2015 at 19:08, Ramana Radhakrishnan wrote: > > > On 01/10/15 17:18, Marek Polacek wrote: >> On Thu, Oct 01, 2015 at 11:02:09AM -0400, David Edelsohn wrote: >>> On Thu, Oct 1, 2015 at 10:49 AM, Marek Polacek wrote: Joseph reminded me that I had forgotten about this patch. As men

[PR other/65021] mkoffloads -save-temps handling, and cleanup cleanup (was: lto wrapper verboseness)

Hi! In a similar vein to the earlier patch to "Pass on the verbose flag "-v" to/in the mkoffloads", here is a patch to make the mkoffloads handle "-save-temps", and this patch also happens to address , "nvptx mkoffload doesn't clean up its temporary files". OK for tru

Re: [Patch 2/2 ARM/AArch64] Add a new Cortex-A53 scheduling model

On 1 October 2015 at 11:41, James Greenhalgh wrote: > On Thu, Oct 01, 2015 at 09:33:07AM +0100, Marcus Shawcroft wrote: >> On 25/09/15 08:59, James Greenhalgh wrote: >> > >> > Hi, >> > >> > This patch introduces a new scheduling model for Cortex-A53. >> > >> > Bootstrapped and tested on arm-none-l

Re: [AARCH64] Add missing entries in iterator vwcore

On Thu, Oct 01, 2015 at 09:41:20PM +0100, Kugan wrote: > Hi, > > In "aarch64_get_lane" operand 0 is VEL, so for %0, > iterator vwcore should (?) support all the modes in VEL. > > Ran into following error with a local patch for an existing test case. > However it can also be reproduced with the a

Re: [Patch 2/2 ARM/AArch64] Add a new Cortex-A53 scheduling model

On Mon, Oct 05, 2015 at 11:07:45AM +0100, Christophe Lyon wrote: > On 1 October 2015 at 11:41, James Greenhalgh wrote: > > On Thu, Oct 01, 2015 at 09:33:07AM +0100, Marcus Shawcroft wrote: > >> On 25/09/15 08:59, James Greenhalgh wrote: > >> > > >> > Hi, > >> > > >> > This patch introduces a new s

Re: [PATCH, ARM] Cleanup attr_thumb-static2.c test directives

Hi Christian, On 30/09/15 11:25, Christian Bruel wrote: On 09/30/2015 10:48 AM, Christian Bruel wrote: Change the test directive to avoid the awkward thumb1 useless skip and relax the required platform Passes for arm-eabi-none with default configure options. sorry, resent clear :-) This

Replace REAL_VALUES_EQUAL with real_equal

Richard B suggested we should replace dconsthalf etc. with dconst<1, 2> (). When I tried that, the extra comma caused problems with some lingering uses of the old target macros for handling reals (e.g. REAL_ARITHMETIC instead of real_arithmetic), since the constant was then treated as two macro pa

Remove remaining uses of REAL_VALUES_IDENTICAL

This patch continues the removal of real-related macros. We already had both the old-style REAL_VALUES_IDENTICAL and the new-style real_identical, so this patch replaces all remaining uses of the former with the latter. Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by building

Replace REAL_VALUES_LESS with real_less

This patch continues the removal of real-related macros by replacing REAL_VALUES_LESS with real_less. Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by building one target per CPU directory and checking that there were no new warnings and no changes in testsuite output at -O2.

Remove remaining uses of REAL_ARITHMETIC

This patch replaces all remaining uses of the old target macro REAL_ARITHMETIC with calls to the (now generic) real_arithmetic function. Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by building one target per CPU directory and checking that there were no new warnings and no c

Remove remaining uses of CONST_DOUBLE_FROM_REAL_VALUE

This patch replaces all uses of CONST_DOUBLE_FROM_REAL_VALUE with the already-existing const_double_from_real_value. Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by building one target per CPU directory and checking that there were no new warnings and no changes in testsuite

Remove REAL_VALUE_FROM_CONST_DOUBLE

To maintain symmetry after the previous removal of CONST_DOUBLE_FROM_REAL_VALUE, this patch also gets rid of REAL_VALUE_FROM_CONST_DOUBLE. All the macro did was copy the contents of CONST_DOUBLE_REAL_VALUE into a temporary real_value structure. In many cases there was no need for this temporary a

Re: [PATCH 2/4] [ARM] Add attribute/pragma target fpu=

Hi Christian, Sorry for the delay. On 14/09/15 11:47, Christian Bruel wrote: This patch defines and uses accessors for the current fpu type fields, based on switchable arm_fpu_index rather than defuncted arm_fpu_desc. Christian + if (TARGET_SOFT_FLOAT) +arm_fpu_attr = FPU_NONE; + else

Re: [PATCH 1/4] [ARM] Add attribute/pragma target fpu=

On 16/09/15 10:29, Christian Bruel wrote: Maybe there is just dirt on my screen or my graphic-memory is broken, but I see an odd character between iWMMXt and and? Thanks Bernhard, Resent to remove this malicious sneaky ` character in the string error message. I keep forgetting if it's a c

Re: [PATCH] Unswitching outer loops.

On Wed, Sep 30, 2015 at 12:46 PM, Yuri Rumyantsev wrote: > Hi Richard, > > I re-designed outer loop unswitching using basic idea of 23855 patch - > hoist invariant guard if loop is empty without guard. Note that this > was added to loop unswitching pass with simple modifications - using > another

Re: Replace REAL_VALUES_EQUAL with real_equal

On Mon, Oct 5, 2015 at 12:41 PM, Richard Sandiford wrote: > Richard B suggested we should replace dconsthalf etc. with > dconst<1, 2> (). When I tried that, the extra comma caused problems > with some lingering uses of the old target macros for handling reals > (e.g. REAL_ARITHMETIC instead of re

Re: Replace REAL_VALUES_LESS with real_less

On Mon, Oct 5, 2015 at 12:43 PM, Richard Sandiford wrote: > This patch continues the removal of real-related macros by > replacing REAL_VALUES_LESS with real_less. > > Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by > building one target per CPU directory and checking that th

Re: Remove remaining uses of REAL_VALUES_IDENTICAL

On Mon, Oct 5, 2015 at 12:43 PM, Richard Sandiford wrote: > This patch continues the removal of real-related macros. > We already had both the old-style REAL_VALUES_IDENTICAL and the > new-style real_identical, so this patch replaces all remaining > uses of the former with the latter. > > Bootstra

Re: [PATCH 3/4] [ARM] Add attribute/pragma target fpu=

Hi Christian, On 14/09/15 12:39, Christian Bruel wrote: This patch splits the neon_builtins initialization into 2 internals functions. One for NEON and one for CRYPTO, each one guarded by its own predicate. arm_init_neon_builtins is now global to be called from arm_valid_target_attribute_tree if

Re: Remove remaining uses of REAL_ARITHMETIC

On Mon, Oct 5, 2015 at 12:44 PM, Richard Sandiford wrote: > This patch replaces all remaining uses of the old target macro > REAL_ARITHMETIC with calls to the (now generic) real_arithmetic > function. > > Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by > building one target p

Re: using scratchpads to enhance RTL-level if-conversion: the new patch now passes bootstrap with the default BUILD_CONFIG [i.e. no stage2-to-stage3 comparison errors even with debugging info off in s

This is currently not really reviewable due to broken indentation, possibly due to whitespace damage from your mailer or not following coding guidelines. Please ensure your code is formatted the same way as all other code in gcc. I'll point out some of the problems, but please investigate ht

Re: Remove remaining uses of CONST_DOUBLE_FROM_REAL_VALUE

On Mon, Oct 5, 2015 at 12:45 PM, Richard Sandiford wrote: > This patch replaces all uses of CONST_DOUBLE_FROM_REAL_VALUE > with the already-existing const_double_from_real_value. > > Bootstrapped & regression-tested on x86_64-linux-gnu. Also tested by > building one target per CPU directory and c

Re: Remove REAL_VALUE_FROM_CONST_DOUBLE

On Mon, Oct 5, 2015 at 12:47 PM, Richard Sandiford wrote: > To maintain symmetry after the previous removal of > CONST_DOUBLE_FROM_REAL_VALUE, this patch also gets rid of > REAL_VALUE_FROM_CONST_DOUBLE. All the macro did was copy the > contents of CONST_DOUBLE_REAL_VALUE into a temporary real_val

[Patch ARM/ AArch64] Fix typo in vcvt_f16.c testcase .

Hi, This test worked by accident. While looking at why this was failing randomly in my builds for arm-none-eabi, I discovered a bug in the way in which the testcases were written up in this case. Tested on arm-none-eabi cross fixing the issues that I was seeing with this test. Applied to trun

Re: [PATCH] Remove gimplifier use from PRE

On Thu, 1 Oct 2015, Richard Biener wrote: > > The following patch from the match-and-simplify branch removes > gimplifier use from PRE replacing it with use of the gimple_build API > building GIMPLE directly. > > Bootstrapped on x86_64-unknown-linux-gnu, testing in progress. The 5th (or so) ref

Re: [PATCH] Fix PR67783, quadraticness in IPA inline analysis

On Thu, 1 Oct 2015, Richard Biener wrote: > > The following avoids quadraticness in the loop depth by only considering > loop header defs as IVs for the analysis of the loop_stride predicate. > This will miss cases like > > foo (int inv) > { > for (i = inv; i < n; ++i) > { > int derived_i

Re: [AArch64] [TLSIE][2/2] Implement TLS IE for tiny model

Hi Jiong, I was looking at another bug and in the process of auditing our code spotted an issue with this patch from back in June... On Fri, Jun 19, 2015 at 10:15:38AM +0100, Jiong Wang wrote: > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 8b061ba..be9da5b 10

Re: [PATCH] SH FDPIC backend support

On Sun, 2015-10-04 at 22:16 -0400, Rich Felker wrote: > This is FDPIC-specific. Because there is fundamentally no way for a > function to find its own GOT (it has one GOT for each process using > the code containing the function), its GOT address has to be a > (hidden) argument to the function whic

Re: [PATCH] Remove restriction for remote testing

Ping. On 09/28/2015 07:35 AM, James Norris wrote: Hi, The attached patch fixes a problem when doing remote testing. Specifically, testing of the atomic tests found in gcc/atomic. The code in atomic_init precludes the setting of the variable 'link_flags' when doing remote testing. The conditiona

[PATCH 2/2][ARC] Add support for ARCv2 CPUs

Just realized this patch haven't went thru to the mailing list. Reposted. This patch adds basic support (libgcc) for Synopsys' ARCv2 CPUs. Can this be committed? Thanks, Claudiu ChangeLog: 2015-08-28 Claudiu Zissulescu * config/arc/dp-hack.h: Add support for ARCHS.

Re: [PR other/65021] mkoffloads -save-temps handling, and cleanup cleanup

On 10/05/2015 12:04 PM, Thomas Schwinge wrote: In a similar vein to the earlier patch to "Pass on the verbose flag "-v" to/in the mkoffloads", here is a patch to make the mkoffloads handle "-save-temps", and this patch also happens to address , "nvptx mkoffload doesn'

Re: [PATCH] Remove restriction for remote testing

On 10/05/2015 02:00 PM, James Norris wrote: Ping. As I said previously, I think appending "-latomic" unconditionally in atomic_init is probably a better solution because I'm not convinced that the things atomic_link_flags does are appropriate in a remote host situation. Bernd

Re: Do not use TYPE_CANONICAL in useless_type_conversion

+ /* For aggregates compare only the size and mode. Accesses to fields do have + a type information by themselves and thus we only care if we can i.e. + use the types in move operations. */ else if (AGGREGATE_TYPE_P (inner_type) && TREE_CODE (inner_type) == TREE_CODE (out

Re: [PATCH] Unswitching outer loops.

Thanks Richard. I'd like to answer on your last comment related to using of exit edge argument for edge that skips loop. Let's consider the following test-case: #include #define N 32 float *foo(int ustride, int size, float *src) { float *buffer, *p; int i, k; if (!src) return NULL;

Re: [AArch64] [TLSIE][2/2] Implement TLS IE for tiny model

James Greenhalgh writes: > Hi Jiong, > > I was looking at another bug and in the process of auditing our code > spotted an issue with this patch from back in June... > > On Fri, Jun 19, 2015 at 10:15:38AM +0100, Jiong Wang wrote: >> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/

Re: C PATCH for c/65345 (file-scope _Atomic expansion with floats)

On Sat, Oct 03, 2015 at 08:58:19PM -0400, David Edelsohn wrote: > The bug was not x86-specific. The fix happens to be in > target-specific code, but that's the luck of the draw. Numerous other > GCC developers have fixed bugs or added features that required tweaks > to all ports. Not all targets

[PATCH] Clear SSA_NAME_ANTI_RANGE_P when appropriate (PR tree-optimization/67821)

Here, we were crashing on an assert in duplicate_ssa_name_range_info: 506 gcc_assert (!SSA_NAME_ANTI_RANGE_P (name)); The problem is that reset_flow_sensitive_info wasn't clearing the SSA_NAME_ANTI_RANGE_P flag; I don't think NULL SSA_NAME_RANGE_INFO can ever describe an anti-range... Bootstra

Re: [patch 0/3] Header file reduction.

On 10/02/2015 04:22 AM, Andrew MacLeod wrote: The patches are generated by a pair of tools. * gcc-order-includes goes through the headers and canonically reorders some of our more common/troublesome headers and removes any duplicates. This includes headers which are included by other headers.

Re: [PATCH] Clear SSA_NAME_ANTI_RANGE_P when appropriate (PR tree-optimization/67821)

On Mon, 5 Oct 2015, Marek Polacek wrote: > Here, we were crashing on an assert in duplicate_ssa_name_range_info: > > 506 gcc_assert (!SSA_NAME_ANTI_RANGE_P (name)); > > The problem is that reset_flow_sensitive_info wasn't clearing the > SSA_NAME_ANTI_RANGE_P flag; I don't think NULL SSA_NAME_R

Re: [patch 0/3] Header file reduction.

On Mon, Oct 5, 2015 at 3:27 PM, Bernd Schmidt wrote: > On 10/02/2015 04:22 AM, Andrew MacLeod wrote: >> >> The patches are generated by a pair of tools. >> * gcc-order-includes goes through the headers and canonically reorders >> some of our more common/troublesome headers and removes any duplicat

Re: [PR other/65021] mkoffloads -save-temps handling, and cleanup cleanup

Hi Bernd! On Mon, 5 Oct 2015 14:12:06 +0200, Bernd Schmidt wrote: > On 10/05/2015 12:04 PM, Thomas Schwinge wrote: > > In a similar vein to the earlier patch to "Pass on the verbose flag "-v" > > to/in the mkoffloads", here is a patch to make the mkoffloads handle > > "-save-temps", and this patc

Re: [PATCH] Clear SSA_NAME_ANTI_RANGE_P when appropriate (PR tree-optimization/67821)

On Mon, Oct 05, 2015 at 04:08:05PM +0200, Richard Biener wrote: > On Mon, 5 Oct 2015, Marek Polacek wrote: > > > Here, we were crashing on an assert in duplicate_ssa_name_range_info: > > > > 506 gcc_assert (!SSA_NAME_ANTI_RANGE_P (name)); > > > > The problem is that reset_flow_sensitive_info w

Re: [PATCH] Clear SSA_NAME_ANTI_RANGE_P when appropriate (PR tree-optimization/67821)

On Mon, 5 Oct 2015, Marek Polacek wrote: > On Mon, Oct 05, 2015 at 04:08:05PM +0200, Richard Biener wrote: > > On Mon, 5 Oct 2015, Marek Polacek wrote: > > > > > Here, we were crashing on an assert in duplicate_ssa_name_range_info: > > > > > > 506 gcc_assert (!SSA_NAME_ANTI_RANGE_P (name)); >

Re: Cache reals for 1/4, 1/6 and 1/9

Richard Biener writes: > On Thu, Oct 1, 2015 at 3:59 PM, Bernd Schmidt wrote: >> On 10/01/2015 03:51 PM, Richard Sandiford wrote: >>> >>> We have a global 1/2 and a cached 1/3, but recalculate 1/4, 1/6 and 1/9 >>> each time we need them. That seems a bit arbitrary and makes the folding >>> code

Re: [PATCH] Clear SSA_NAME_ANTI_RANGE_P when appropriate (PR tree-optimization/67821)

On Mon, Oct 05, 2015 at 04:26:49PM +0200, Richard Biener wrote: > > > Otherwise other setters of SSA_NAME_RANGE_INFO would need to make > > > sure SSA_NAME_ANTI_RANGE_P is cleared as well. > > > > They mostly do, if I'm looking right, e.g. > > tree-ssa-phiopt.c:1016 > > tree-ssa-loop-im.c:1224 >

Generalize gimple_val_nonnegative_real_p

The upcoming patch to move sqrt and cbrt simplifications to match.pd caused a regression because the (abs @0)->@0 simplification didn't trigger for: (abs (convert (abs X))) The simplification is based on tree_expr_nonnegative_p, which is pretty weak for gimple (it gives up if it sees an SSA_N

Re: Cache reals for 1/4, 1/6 and 1/9

On 10/05/2015 04:47 PM, Richard Sandiford wrote: @@ -9536,7 +9520,7 @@ fold_builtin_classify (location_t loc, tree fndecl, tree arg, int builtin_index) { r = TREE_REAL_CST (arg); if (real_isinf (&r)) - return real_compare (GT_EXPR, &r, &dconst0) +

Re: C PATCH for c/65345 (file-scope _Atomic expansion with floats)

On Sat, 3 Oct 2015, David Edelsohn wrote: > It's poor form to fix a bug only on x86 that is common to all targets > and leave the problem "as an exercise for the reader" for all other > targets -- essentially banishing the other targets to second-class > status with respect to conformance -- espec

Re: using scratchpads to enhance RTL-level if-conversion: the new patch now passes bootstrap with the default BUILD_CONFIG [i.e. no stage2-to-stage3 comparison errors even with debugging info off in s

Oh, one other thing. To be able to include your code we need to have a copyright assignment to the FSF from you. I see one previous commit from you, but only a trivial one and with a corporate email address. Have you gone through the copyright assignment process? Bernd

Move sqrt and cbrt simplifications to match.pd

This patch moves the sqrt and cbrt simplification rules to match.pd. builtins.c now only does the constant folding. Bootstrapped & regression-tested on x86_64-linux-gnu. OK to install? Thanks, Richard gcc/ * builtins.c (fold_builtin_sqrt, fold_builtin_cbrt): Delete. (fold_built

Re: Cache reals for 1/4, 1/6 and 1/9

Bernd Schmidt writes: > On 10/05/2015 04:47 PM, Richard Sandiford wrote: >> @@ -9536,7 +9520,7 @@ fold_builtin_classify (location_t loc, tree fndecl, >> tree arg, int builtin_index) >> { >>r = TREE_REAL_CST (arg); >>if (real_isinf (&r)) >> -return real_compare (GT_EXP

Re: RFC: PATCH for front end parts of C++ transactional memory TS

On 10/05/2015 05:00 AM, Andreas Schwab wrote: Jason Merrill writes: diff --git a/gcc/testsuite/g++.dg/tm/eh1.C b/gcc/testsuite/g++.dg/tm/eh1.C new file mode 100644 index 000..1561211 --- /dev/null +++ b/gcc/testsuite/g++.dg/tm/eh1.C @@ -0,0 +1,10 @@ +// A handler can involve a transaction-

Re: Cache reals for 1/4, 1/6 and 1/9

On 10/05/2015 05:22 PM, Richard Sandiford wrote: Bernd Schmidt writes: On 10/05/2015 04:47 PM, Richard Sandiford wrote: @@ -9536,7 +9520,7 @@ fold_builtin_classify (location_t loc, tree fndecl, tree arg, int builtin_index) { r = TREE_REAL_CST (arg); if (real_isinf

Re: [PATCH] Fix PR67783, quadraticness in IPA inline analysis

> On Thu, 1 Oct 2015, Richard Biener wrote: > > > > > The following avoids quadraticness in the loop depth by only considering > > loop header defs as IVs for the analysis of the loop_stride predicate. > > This will miss cases like > > > > foo (int inv) > > { > > for (i = inv; i < n; ++i) > >

Re: Do not use TYPE_CANONICAL in useless_type_conversion

> >+ /* For aggregates compare only the size and mode. Accesses to fields do > >have > >+ a type information by themselves and thus we only care if we can i.e. > >+ use the types in move operations. */ > >else if (AGGREGATE_TYPE_P (inner_type) > >&& TREE_CODE (inner_type) ==

Re: [PATCH] Add verifier for leaked SSA names

On 10/05/2015 02:56 AM, Richard Biener wrote: I was building the verification step into the ssa name manager. Essentially at the point where we flush from the pending to the free list, we should have a consistent state. Yeah, though when SSA verifiers run the state should also be consistent and

[PATCH, i386, AVX512] PR target/67849: Avoid upper-bank registers when splitting vec_extract_lo instruction.

This patch addresses PR target/67849. Given a machine that does not support AVX512VL, following "else" branch for vec_exract_lo insn may result in a split using YMMs from upper-bank, hence invalid assembly. Tuning define_insn pattern and define_split constraints eliminates this problem. Please tak

Re: [PATCH, i386, AVX512] PR target/67849: Avoid upper-bank registers when splitting vec_extract_lo instruction.

On Mon, Oct 5, 2015 at 5:54 PM, Alexander Fomin wrote: > This patch addresses PR target/67849. Given a machine that does not > support AVX512VL, following "else" branch for vec_exract_lo insn > may result in a split using YMMs from upper-bank, hence invalid > assembly. Tuning define_insn pattern a

[gomp4] [nvptx] Don't explicitly pass "-lgomp" to the offload compiler (was: nvptx offloading linking)

Hi! On Wed, 13 May 2015 22:11:36 +0200, I wrote: > On Wed, 22 Apr 2015 17:08:26 +0200, Bernd Schmidt > wrote: > > On 04/21/2015 05:58 PM, Jakub Jelinek wrote: > > > > > suggests that while it is nice that when building nvptx accel compiler > > > we build libgcc.a, libc.a, libm.a, libgfortran.a

Re: RFC: Patch to allow spill slot alignment greater than the stack alignment

On Mon, 2015-10-05 at 10:41 +0200, Bernd Schmidt wrote: > On 10/02/2015 10:57 PM, Steve Ellcey wrote: > > I have spent some time trying to do dynamic stack alignment on MIPS and had > > considerable trouble. The problems are mainly due to the dwarf based stack > > unwinding and setjmp/longjmp usag

[PATCH] Fix ICE for SIMD clones usage in LTO

Hi, When SIMD clone is created original function may be defined in another partition. In this case SIMD clone also has to have in_other_partition flag. Now it doesn't and we get an ICE. This patch fixes it. Bootstrapped and regtested for x86_64-unknown-linux-gnu. OK for trunk? Thanks, Ily

Re: RFC: Patch to allow spill slot alignment greater than the stack alignment

On Mon, Oct 5, 2015 at 9:10 AM, Steve Ellcey wrote: > On Mon, 2015-10-05 at 10:41 +0200, Bernd Schmidt wrote: >> On 10/02/2015 10:57 PM, Steve Ellcey wrote: >> > I have spent some time trying to do dynamic stack alignment on MIPS and had >> > considerable trouble. The problems are mainly due to t

Re: [patch] Update template instantiation documentation

On 03/10/15 10:44 -0600, Sandra Loosemore wrote: On 10/03/2015 06:47 AM, Jonathan Wakely wrote: https://gcc.gnu.org/onlinedocs/gcc/Template-Instantiation.html currently says that using -frepo "is your best option for application code written for the Borland model, as it just works." That was tr

Re: [PATCH] Clear SSA_NAME_ANTI_RANGE_P when appropriate (PR tree-optimization/67821)

On October 5, 2015 4:46:44 PM GMT+02:00, Marek Polacek wrote: >On Mon, Oct 05, 2015 at 04:26:49PM +0200, Richard Biener wrote: >> > > Otherwise other setters of SSA_NAME_RANGE_INFO would need to make >> > > sure SSA_NAME_ANTI_RANGE_P is cleared as well. >> > >> > They mostly do, if I'm looking

Re: [PATCH] Clear SSA_NAME_ANTI_RANGE_P when appropriate (PR tree-optimization/67821)

On Mon, Oct 05, 2015 at 06:27:53PM +0200, Richard Biener wrote: > On October 5, 2015 4:46:44 PM GMT+02:00, Marek Polacek > wrote: > >On Mon, Oct 05, 2015 at 04:26:49PM +0200, Richard Biener wrote: > >> > > Otherwise other setters of SSA_NAME_RANGE_INFO would need to make > >> > > sure SSA_NAME_AN

Re: [patch] Update template instantiation documentation

Looks good to me, thanks. Jason

Re: RFC: Patch to allow spill slot alignment greater than the stack alignment

On Mon, 2015-10-05 at 09:21 -0700, H.J. Lu wrote: > On Mon, Oct 5, 2015 at 9:10 AM, Steve Ellcey wrote: > > There probably is some way to get dynamic stack alignment to work on > > MIPS, but I am not sure I can do it. The only platform that I see that > > uses dynamic stack alignment is x86. I

Re: [C++ Patch] PR 53856

Hi, On 09/24/2015 03:24 PM, Jason Merrill wrote: On 09/22/2015 03:31 PM, Paolo Carlini wrote: msg = G_("default template arguments may not be used in " "partial specializations"); + else if (current_class_type && !CLASSTYPE_IS_TEMPLATE (current_class_type)) +/* Per [temp.p

Re: RFC: Patch to allow spill slot alignment greater than the stack alignment

On Mon, Oct 5, 2015 at 9:46 AM, Steve Ellcey wrote: > On Mon, 2015-10-05 at 09:21 -0700, H.J. Lu wrote: >> On Mon, Oct 5, 2015 at 9:10 AM, Steve Ellcey wrote: > >> > There probably is some way to get dynamic stack alignment to work on >> > MIPS, but I am not sure I can do it. The only platform t

Re: Cache reals for 1/4, 1/6 and 1/9

Bernd Schmidt writes: > On 10/05/2015 05:22 PM, Richard Sandiford wrote: >> Bernd Schmidt writes: >>> On 10/05/2015 04:47 PM, Richard Sandiford wrote: @@ -9536,7 +9520,7 @@ fold_builtin_classify (location_t loc, tree fndecl, tree arg, int builtin_index) {

Re: RFC: Patch to allow spill slot alignment greater than the stack alignment

On 10/05/2015 06:46 PM, Steve Ellcey wrote: One example of an issue I have run into is with the DWARF unwind generation and 'Rule 16' in dwarf2cfi.c. It assumes the AND instruction has an integer constant argument but MIPS can't do an AND with a constant like -16 so it has to put it in a regist

Re: Cache reals for 1/4, 1/6 and 1/9

On 10/05/2015 07:00 PM, Richard Sandiford wrote: If my original patch isn't acceptable, I thought I'd approved it. another old-school way of doing it would be to have a .def file of all the constants that we want. They could then all be global variables, rather than having some that are and

Re: [PATCH, rs6000] Fix PR target/67808, LRA ICE on double to long double conversion

On Fri, Oct 02, 2015 at 02:04:48PM -0500, Peter Bergner wrote: > PR67808 exposes a problem with the constraints in the *extenddftf2_internal > pattern, in that it allows TFmode operands to occupy Altivec registers > which they are not allowed to do. Reload was able to work around the > problem, bu

RE: [PATCH, MIPS] Frame header optimization for MIPS O32 ABI

On Mon, 2015-09-28 at 22:10 +, Moore, Catherine wrote: > Hi Steve, I'm sorry for the delay in reviewing this patch. > Some changes have been committed upstream (see revision #227941) that will > require updates to this patch. > Please post the update for review. Other comments are embedded.

Re: [C++ Patch] PR 53856

On 10/05/2015 12:50 PM, Paolo Carlini wrote: + else if (!current_class_type || CLASSTYPE_IS_TEMPLATE (current_class_type)) +msg = G_("default argument for template parameter for class enclosing %qD"); Why would this be right when !current_class_type? Jason

Re: Cache reals for 1/4, 1/6 and 1/9

On Mon, 5 Oct 2015, Richard Sandiford wrote: I do believe you still have some code growth since the inline dconst function always expands code that will initialize the constant. IMO that's not desirable. I don't disagree. I find dconst0 much easier to read than dconst<0> (). In some ways I wa

[PATCH v2, i386]: Enable -mstackrealign and 'force_align_arg_pointer' attribute for x86_64

On Sun, Oct 4, 2015 at 5:26 PM, Uros Bizjak wrote: > As shown in PR 66697 [1] and WineHQ bug [2], an application can > misalign incoming stack to less than ABI mandated 16 bytes. While it > is possible to use -mincoming-stack-boundary=2 (= 4 bytes) for 32 bit > targets to emit stack realignment

Re: [PATCH, rs6000] Fix PR target/67808, LRA ICE on double to long double conversion

On Mon, 2015-10-05 at 13:12 -0400, Michael Meissner wrote: > I have attached a better version of the patch. I'll note that I have not committed the earlier patch and will hold off while we sort out what is best here. > This gives the constraints: > > #1: op0 = m, op1 = d, op2 = d > #2: o

Re: [C++ Patch] PR 53856

Hi, On 10/05/2015 07:10 PM, Jason Merrill wrote: On 10/05/2015 12:50 PM, Paolo Carlini wrote: + else if (!current_class_type || CLASSTYPE_IS_TEMPLATE (current_class_type)) +msg = G_("default argument for template parameter for class enclosing %qD"); Why would this be right when !current

Re: [C++ Patch] PR 53856

OK. Jason

Re: RFC: Patch to allow spill slot alignment greater than the stack alignment

On Oct 5, 2015, at 9:46 AM, Steve Ellcey wrote: > One example of an issue I have run into is with the DWARF unwind > generation and 'Rule 16' in dwarf2cfi.c. It assumes the AND instruction > has an integer constant argument but MIPS can't do an AND with a > constant like -16 so it has to put it i

Go patch committed: Update Unicode letters table to Unicode 8.0.0

This patch by Chris Manghane updates the Go frontend unicode letters table to Unicode 8.0.0. This fixes https://golang.org/issue/12322 . Bootstrapped and ran Go testsuite on x86_64-unknown-linux-gnu. Committed to mainline. Ian Index: gospec.c ==

Re: Cache reals for 1/4, 1/6 and 1/9

On Oct 5, 2015, at 7:47 AM, Richard Sandiford wrote: > - return real_equal (&TREE_REAL_CST (expr), &dconst0) > + return real_equal (&TREE_REAL_CST (expr), &dconst<0> ()) On behalf of mere mortals, hiding the syntax &dconst<0> () into a header file as in implementation detail is entirel

Re: [patch] Update template instantiation documentation

On 10/05/2015 10:40 AM, Jason Merrill wrote: Looks good to me, thanks. Jason Looks good to me, too. -Sandra

Re: Cache reals for 1/4, 1/6 and 1/9

On October 5, 2015 8:04:59 PM GMT+02:00, Mike Stump wrote: >On Oct 5, 2015, at 7:47 AM, Richard Sandiford > wrote: >> - return real_equal (&TREE_REAL_CST (expr), &dconst0) >> + return real_equal (&TREE_REAL_CST (expr), &dconst<0> ()) > >On behalf of mere mortals, hiding the syntax &dcon

Re: [PATCH] Remove restriction for remote testing

On Sep 28, 2015, at 5:35 AM, James Norris wrote: > The attached patch fixes a problem when doing remote testing. > Specifically, testing of the atomic tests found in gcc/atomic. > The code in atomic_init precludes the setting of the variable > 'link_flags' when doing remote testing. The conditiona

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