Hi,
Currently most non-target specific options are skipped when crossing the
LTO/offload processing border, however since there are still quite a
number of warning calls in many target backends, it makes sense to
save and propagate the associated options, to preserve consistency in warning
behavior
Dear All,
The attached patch more or less implements the assignment of
expressions to the result of a pointer function. To wit:
my_ptr_fcn (arg1, arg2...) = expr
arg1 would usually be the target, pointed to by the function. The
patch parses these statements and resolves them into:
temp_ptr => m
It helps to attach the patch :-)
Paul
On 6 September 2015 at 13:42, Paul Richard Thomas
wrote:
> Dear All,
>
> The attached patch more or less implements the assignment of
> expressions to the result of a pointer function. To wit:
>
> my_ptr_fcn (arg1, arg2...) = expr
>
> arg1 would usually be t
Hi,
we observed sporadic failures of the following two test cases (see PR64078):
c-c++-common/ubsan/object-size-9.c and c-c++-common/ubsan/object-size-10.c
For object-size-9.c this happens in a reproducible way when -fpic option is
used:
If that option is used, it is slightly less desirable to i
This a new version of the patch posted in
https://gcc.gnu.org/ml/gcc-patches/2015-08/msg00226.html. I have done
more testing and spitted the patch to make it more easier to review.
There are still couple of issues to be addressed and I am working on them.
1. AARCH64 bootstrap now fails with the c
This patch adds support for new tree code SEXT_EXPR.
gcc/ChangeLog:
2015-09-07 Kugan Vivekanandarajah
* cfgexpand.c (expand_debug_expr): Handle SEXT_EXPR.
* expr.c (expand_expr_real_2): Likewise.
* fold-const.c (int_const_binop_1): Likewise.
* tree-cfg.c (veri
This pass applies type promotion to SSA names in the function and
inserts appropriate truncations to preserve the semantics. Idea of this
pass is to promote operations such a way that we can minimize generation
of subreg in RTL, that intern results in removal of redundant zero/sign
extensions.
g
This patch tree-vrp handling and optimization for ZEXT_EXPR.
gcc/ChangeLog:
2015-09-07 Kugan Vivekanandarajah
* tree-vrp.c (extract_range_from_binary_expr_1): Handle SEXT_EXPR.
(simplify_bit_ops_using_ranges): Likewise.
(simplify_stmt_using_ranges): Likewise.
>From 7
For the following testcase (compiling with -O1; -O2 works fine), we have
a stmt with stm_code SSA_NAME (_7 = _ 6) and for which _6 is defined by
a GIMPLE_CALL. In this case, we are using wrong SUNREG promoted mode
resulting in wrong code. Simple SSA_NAME copes are generally optimized
but when the
Allow GIMPLE_DEBUG with values in promoted register.
gcc/ChangeLog:
2015-09-07 Kugan Vivekanandarajah
* expr.c (expand_expr_real_1): Set proper SUNREG_PROMOTED_MODE for
SSA_NAME that was set by GIMPLE_CALL and assigned to another
SSA_NAME of same type.
>From a28de63bc
Allow GIMPLE_DEBUG with values in promoted register.
gcc/ChangeLog:
2015-09-07 Kugan Vivekanandarajah
* expr.c (expand_expr_real_1): Set proper SUBREG_PROMOTED_MODE for
SSA_NAME that was set by GIMPLE_CALL and assigned to another
SSA_NAME of same type.
>From a28de63bc
AARCH64 bootstrap problem that started happening with the commit
94f92c36a83d66a893c3bc6f00a038ba3dbe2a6f. simplify-rtx.c mis-compiled in
stage due to this fwprop.c is failing. It looks to me that there is a
latent issue which gets exposed my patch. I can also reproduce this in
x86_64 if I use the
gcc/testsuite/ChangeLog:
2015-09-07 Kugan Vivekanandarajah
* gcc.target/arm/mla-2.c: Scan for wider mode operation.
* gcc.target/arm/wmul-1.c: Likewise.
* gcc.target/arm/wmul-2.c: Likewise.
* gcc.target/arm/wmul-3.c: Likewise.
* gcc.target/arm/wmul-9.c
This patch is designed to address code that was not being vectorized due
to missing widening patterns in the aarch64 backend. Code such as:
int t6(int len, void * dummy, short * __restrict x)
{
len = len & ~31;
int result = 0;
__asm volatile ("");
for (int i = 0; i < len; i++)
result
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