On Tue, Feb 03, 2015 at 10:23:22PM -0500, David Edelsohn wrote:
> On Tue, Feb 3, 2015 at 5:55 PM, Andreas Schwab wrote:
> > FAIL: gcc.dg/builtins-58.c scan-assembler-not pow
> >
> > $ grep pow builtins-58.s
> > .machine power4
>
> Any suggestions?
Perhaps tighten up the regexp, like (unt
On Wed, Feb 04, 2015 at 04:11:03AM -0200, Alexandre Oliva wrote:
> for gcc/ChangeLog
>
> PR debug/64817
> * simplify-rtx.c (simplify_binary_operation_1): Rewrite
> simplification of XOR of AND to not allocate new rtx before
> committing to a simplification.
Ok, thanks.
On Wed, Feb 04, 2015 at 03:56:56AM -0200, Alexandre Oliva wrote:
> for gcc/ChangeLog
>
> PR debug/64817
> * cfgexpand.c (expand_debug_expr): Compute unsignedp from
> operands for tcc_comparison exprs. Fix typos.
>
> for gcc/testsuite/ChangeLog
>
> PR debug/64817
>
> From: Jakub Jelinek [mailto:ja...@redhat.com]
> Sent: Wednesday, February 04, 2015 3:54 PM
>
> Richard already acked it with the new testcase, so yes, this is ok for the
> trunk (just use today's date).
Oups my bad, I forgot he acked it.
Thanks and best regards.
Thomas
On Wed, Feb 04, 2015 at 04:21:43AM -0200, Alexandre Oliva wrote:
> I'm a bit surprised the gimple layer does not even attempt to simplify
> them, but I didn't try to tackle that, since I was not even sure this
> was a useful optimization. After all, how often do we see xor of and of
> xor of and o
On February 4, 2015 9:35:13 AM CET, Jakub Jelinek wrote:
>On Wed, Feb 04, 2015 at 04:21:43AM -0200, Alexandre Oliva wrote:
>> I'm a bit surprised the gimple layer does not even attempt to
>simplify
>> them, but I didn't try to tackle that, since I was not even sure this
>> was a useful optimizatio
On February 4, 2015 5:49:13 AM CET, Cary Coutant wrote:
>The plugin is not supposed to call release_input_file from the
>claim_file handler. That interface is only for releasing a file
>descriptor obtained via get_input_file during the all_symbols_read
>callback. When the linker calls the claim_fi
On Wed, Feb 04, 2015 at 09:54:53AM +0100, Richard Biener wrote:
> On February 4, 2015 9:35:13 AM CET, Jakub Jelinek wrote:
> >On Wed, Feb 04, 2015 at 04:21:43AM -0200, Alexandre Oliva wrote:
> >> I'm a bit surprised the gimple layer does not even attempt to
> >simplify
> >> them, but I didn't try
> #elif ! (defined (__vxworks))
>
> ^^ __vxworks will not be defined by anything other than a vxworks
> compiler, I'd assume (it is certainly not defined by Darwin toolchains)
>
> extern char **environ;
> return environ;
>
> vvv so I don't see how this case will ever be exercised.
> #
Hi Kaz!
On Wed, 04 Feb 2015 08:41:28 +0900 (JST), Kaz Kojima
wrote:
> Several goacc/acc_on_device tests fail for a few targets:
>
> hppa2.0w-hp-hpux11.11 (PR testsuite/64850)
> https://gcc.gnu.org/ml/gcc-testresults/2015-01/msg02659.html
>
> m68k-unknown-linux-gnu
> https://gcc.gnu.org/ml/gcc-
On Mon, Feb 02, 2015 at 04:32:34PM +0100, Thomas Schwinge wrote:
> Hi!
>
> On Tue, 23 Dec 2014 19:49:35 +0100, I wrote:
> > On Mon, 10 Nov 2014 17:19:57 +0100, Bernd Schmidt
> > wrote:
> > > The scripts (11/11) I've put up on github, along with a hacked up
> > > newlib. These are at [...]
>
>
Hi,
I've observed a FAILURE for gcc.dg/graphite/scop-19.c with fpic:
...
FAIL: gcc.dg/graphite/scop-19.c scan-tree-dump-times graphite "number of SCoPs:
0" 2
...
In the nonpic case, d_growable_string_resize is inlined into
d_growable_string_append_buffer, and we have 2 functions with a loop, w
On February 4, 2015 10:15:30 AM CET, Jakub Jelinek wrote:
>On Wed, Feb 04, 2015 at 09:54:53AM +0100, Richard Biener wrote:
>> On February 4, 2015 9:35:13 AM CET, Jakub Jelinek
>wrote:
>> >On Wed, Feb 04, 2015 at 04:21:43AM -0200, Alexandre Oliva wrote:
>> >> I'm a bit surprised the gimple layer d
On Wed, Feb 04, 2015 at 10:54:54AM +0100, Richard Biener wrote:
> Sure. Of course it's bad that debug stmts use Generic... General
> fold-stmt could do some of the work. Also that debug temps have no
> use-def chains doesn't help too much.
Well, at least right now I believe debug temps work mor
Hi,
I decided to spend some time looking at the large number of guality
test failures on arm. I see a number of fails with
gcc.dg/guality/pr36728-1.c as below. pr36728-2.c also fails in similar
sort of ways. Before I go adjusting too many other tests I'd like to get
some feedback regarding t
On Wed, Feb 04, 2015 at 09:00:57AM +0100, Jakub Jelinek wrote:
> On Tue, Feb 03, 2015 at 10:23:22PM -0500, David Edelsohn wrote:
> > On Tue, Feb 3, 2015 at 5:55 PM, Andreas Schwab
> > wrote:
> > > FAIL: gcc.dg/builtins-58.c scan-assembler-not pow
> > >
> > > $ grep pow builtins-58.s
> > >
These two testcases stopped working on rs6000, since we now emit
".machine power4" and similar pseudo-ops. This fixes it by testing
for "pow" at the end of words only.
Regression checking in progress on powerpc64-linux (where it failed
before); okay if it passes?
Segher
2015-02-04 Segher Boe
Hi,
On 02/02/2015 11:26 PM, Ville Voutilainen wrote:
On 2 February 2015 at 20:50, Ville Voutilainen
wrote:
The modified test has been tested, I'm currently running the full testsuite,
so testing is incomplete. I wanted to send this in asap, since this is a
bad regression.
/cp
2015-02-02 Vill
On Wed, Feb 04, 2015 at 02:14:53AM -0800, Segher Boessenkool wrote:
> These two testcases stopped working on rs6000, since we now emit
> ".machine power4" and similar pseudo-ops. This fixes it by testing
> for "pow" at the end of words only.
>
> Regression checking in progress on powerpc64-linux
Rainer Orth writes:
> Hi Alexandre,
>
>> On Jan 28, 2015, Mike Stump wrote:
>>
>>> On Jan 28, 2015, at 2:27 AM, Rainer Orth
>>> wrote:
There are two ways to fix this:
* Remove the definition of _XOPEN_SOURCE completely. This is slightly
more risky, but more future-proof s
Hello,
The Cortex-A72 is an ARMv8 core with the same architectural features as
the Cortex-A57. This patch adds support for the command line option
-mcpu=cortex-a72 with the same effect as the -mcpu=cortex-a57 option,
only the name being different. It also adds support for the
-mcpu=cortex-a72
> For some TARGET, like ARM THUMB1, the offset in load/store should be nature
> aligned. But in function get_address_cost, when computing max_offset, it
> only tries byte-aligned offsets:
>
> ((unsigned HOST_WIDE_INT) 1 << i) - 1
>
> which can not meet thumb_legitimate_offset_p check called fro
Hello,
The Cortex-A72 is an ARMv8 core with the same architectural features as
the Cortex-A57. This patch adds support for the command line option
-mcpu=cortex-a72 with the same effect as the -mcpu=cortex-a57 option,
with only the name being different. It also adds support for the
-mcpu=corte
On Fri, Jan 16, 2015 at 11:45:40AM +0100, Richard Biener wrote:
> On Thu, Jan 15, 2015 at 7:35 PM, Jeff Law wrote:
> > On 11/20/14 05:33, Bernd Schmidt wrote:
> >>
> >> Now that I've managed to put together and test all the submitted OpenACC
> >> patches I found there was one piece missing. The pr
On 4 February 2015 at 12:22, Paolo Carlini wrote:
> I see that Jason applied the fix to mainline. Today I noticed that this is
> also a regression in the 4_9-branch: shall I regression test the fix there
> too, in case apply and close the bug?
Please do, thanks.
On Sat, Nov 01, 2014 at 12:51:32PM +0100, Bernd Schmidt wrote:
> LTO has a mechanism not to stream out common nodes that are expected to be
> identical on each run. When using LTO to communicate between compilers for
> different targets, the va_list_type_node and related ones must be excluded
> fro
On Wed, Feb 04, 2015 at 11:55:54AM +0100, Jakub Jelinek wrote:
> On Sat, Nov 01, 2014 at 12:51:32PM +0100, Bernd Schmidt wrote:
> > LTO has a mechanism not to stream out common nodes that are expected to be
> > identical on each run. When using LTO to communicate between compilers for
> > different
>
> Changelog:
>
> * gcc.dg/guality/pr36728-1.c: Skip some tests for arm.
>
Segher and I discussed an alternative approach - marking these as "m"
(arg1) , "m" (arg2) etc in the asm blocks also gives us the same
effect and then probably removes the need to rely on such target
markers. I've ju
I think that fix for avx2 part should be backported to 4.8/4.9
What do you think?
On 14 Jan 14:18, Ilya Tocar wrote:
> Hi,
>
> This patch fixes https://gcc.gnu.org/bugzilla/show_bug.cgi?id=64387
> Which was caused by different in predicates between vec_unpacks_hi
> and vec_extract_hi.
> Ok for tr
Ping.
https://gcc.gnu.org/ml/gcc-patches/2015-01/msg00710.html
Thanks,
Kyrill
On 27/01/15 09:45, Kyrill Tkachov wrote:
On 19/01/15 15:46, Kyrill Tkachov wrote:
On 19/01/15 15:44, James Greenhalgh wrote:
On Mon, Jan 12, 2015 at 05:30:46PM +, Andrew Pinski wrote:
On Mon, Jan 12, 2015 at
On Wed, Feb 04, 2015 at 11:03:29AM +, Ramana Radhakrishnan wrote:
> >
> > Changelog:
> >
> > * gcc.dg/guality/pr36728-1.c: Skip some tests for arm.
> >
>
> Segher and I discussed an alternative approach - marking these as "m"
> (arg1) , "m" (arg2) etc in the asm blocks also gives us the s
Hi DJ,
Please can I apply the patch below to fix some RL78 gcc testsuite
failures ?
The patch does two things: Firstly in the RL78 assembler version of
the __addsf3 function it fixes a corner case where rounding up the
fraction results in an overflow into an unused bit. The problem h
On 04/02/2015 11:10, Jakub Jelinek wrote:
On Wed, Feb 04, 2015 at 11:03:29AM +, Ramana Radhakrishnan wrote:
Changelog:
* gcc.dg/guality/pr36728-1.c: Skip some tests for arm.
Segher and I discussed an alternative approach - marking these as "m"
(arg1) , "m" (arg2) etc in the asm b
> > 2015-02-02 Robert Suchanek
> >
> >* gcc.target/mips/loongson-simd.c: Update comment to clarify the
> need
> >for mips_nanlegacy target.
> >
> > diff --git a/gcc/testsuite/gcc.target/mips/loongson-simd.c
> > b/gcc/testsuite/gcc.target/mips/loongson-simd.c
> > index 949632e..9c
On 12 January 2015 at 15:52, Kyrill Tkachov wrote:
> Hi all,
>
> As raised in https://gcc.gnu.org/ml/gcc-patches/2014-12/msg01237.html and
> discussed in that thread, using __builtin_sqrt for vsqrt_f64 may end up in a
> call to the library sqrt at -O0. To avoid that this patch uses a target
> buil
On Sat, Nov 01, 2014 at 12:57:45PM +0100, Bernd Schmidt wrote:
> This is not against current trunk; it applies to gomp-4_0-branch where it is
> one of the necessary parts to make offloading x86->nvptx work. The issue is
> that the LTO file format depends on the machine_modes enum, it needs to
> mat
On Wed, Feb 04, 2015 at 11:33:19AM +, Ramana Radhakrishnan wrote:
> --- a/gcc/testsuite/gcc.dg/guality/pr36728-1.c
> +++ b/gcc/testsuite/gcc.dg/guality/pr36728-1.c
> @@ -49,5 +49,6 @@ main ()
>int l = 0;
>asm ("" : "=r" (l) : "0" (l));
>a = foo (l + 1, l + 2, l + 3, l + 4, l + 5, l
These testcases currently XPASS on most targets and configs, so let's
reduce the noise. Okay for mainline?
Segher
2015-02-04 Segher Boessenkool
gcc/testsuite/
* gcc.dg/guality/pr41447-1.c: Remove xfail.
* gcc.dg/guality/pr41616-1.c: Ditto.
---
gcc/testsuite/gcc.dg/guality
Hi Guys,
I am applying the patch below to extend the MSP430 port of gcc's
auto-recognition of F5 multiply hardware enabled MCUs.
Cheers
Nick
gcc/ChangeLog
2015-02-04 Nick Clifton
* config/msp430/msp430.c (msp430_use_f5_series_hwmult): Add more
prefixes of known F5 using
On Wed, Feb 04, 2015 at 03:48:38AM -0800, Segher Boessenkool wrote:
> These testcases currently XPASS on most targets and configs, so let's
> reduce the noise. Okay for mainline?
Doesn't look like that is the case. obj69 is x86_64, obj70 is i686.
grep '\(41447\|41616\).*execution' obj{69,70}/gcc
Hi,
HAVE_DESIGNATED_INITIALIZERS is not set for C++, so the NAMED_PARAM macros
using it provide false security when we compile aarch64.c. Removing this
is an obvious cleanup and gets rid of some confusing dead code.
This patch removes all the magic macros.
Bootstrapped and tested on aarch64-non
Hi all,
This patch improves the vc patterns in neon.md to use proper RTL
operations rather than UNSPECS.
It is done in a similar way to the analogous aarch64 operations i.e.
vceq is expressed as
(neg (eq (...) (...)))
since we want to write all 1s to the result element when 'eq' holds and
0s
Hi all,
This patch makes use of std::swap in every peephole2 of
aarch64-ldp-stp.md instead of manually swapping rtxen.
No functional change, just a cleanup.
Bootstrapped and tested on aarch64.
I'm proposing this for next stage1 together with the other AArch64 patch
that
moves a couple of pla
On Wed, Feb 04, 2015 at 12:18:29PM +, Kyrill Tkachov wrote:
> Hi all,
>
> This patch makes use of std::swap in every peephole2 of
> aarch64-ldp-stp.md instead of manually swapping rtxen.
> No functional change, just a cleanup.
> Bootstrapped and tested on aarch64.
>
> I'm proposing this for
On 04/02/2015 11:40, Jakub Jelinek wrote:
On Wed, Feb 04, 2015 at 11:33:19AM +, Ramana Radhakrishnan wrote:
--- a/gcc/testsuite/gcc.dg/guality/pr36728-1.c
+++ b/gcc/testsuite/gcc.dg/guality/pr36728-1.c
@@ -49,5 +49,6 @@ main ()
int l = 0;
asm ("" : "=r" (l) : "0" (l));
a = foo
On 4 February 2015 at 12:06, James Greenhalgh wrote:
>
> Hi,
>
> HAVE_DESIGNATED_INITIALIZERS is not set for C++, so the NAMED_PARAM macros
> using it provide false security when we compile aarch64.c. Removing this
> is an obvious cleanup and gets rid of some confusing dead code.
>
> This patch re
On February 4, 2015 11:32:54 AM CET, Eric Botcazou
wrote:
>> For some TARGET, like ARM THUMB1, the offset in load/store should be
>nature
>> aligned. But in function get_address_cost, when computing max_offset,
>it
>> only tries byte-aligned offsets:
>>
>> ((unsigned HOST_WIDE_INT) 1 << i) - 1
On 4 February 2015 at 12:18, Kyrill Tkachov wrote:
> Hi all,
>
> This patch makes use of std::swap in every peephole2 of aarch64-ldp-stp.md
> instead of manually swapping rtxen.
> No functional change, just a cleanup.
> Bootstrapped and tested on aarch64.
>
> I'm proposing this for next stage1 tog
On 4 February 2015 at 10:35, Matthew Wahab wrote:
> Hello,
>
> The Cortex-A72 is an ARMv8 core with the same architectural features as the
> Cortex-A57. This patch adds support for the command line option
> -mcpu=cortex-a72 with the same effect as the -mcpu=cortex-a57 option, only
> the name being
On Wed, Feb 4, 2015 at 12:05 PM, Ilya Tocar wrote:
> I think that fix for avx2 part should be backported to 4.8/4.9
> What do you think?
OK also for branches.
Thanks,
Uros.
On Wed, Feb 4, 2015 at 12:57 PM, Marcus Shawcroft
wrote:
> On 4 February 2015 at 10:35, Matthew Wahab wrote:
>> Hello,
>>
>> The Cortex-A72 is an ARMv8 core with the same architectural features as the
>> Cortex-A57. This patch adds support for the command line option
>> -mcpu=cortex-a72 with the
On Mon, Feb 2, 2015 at 10:39 PM, H.J. Lu wrote:
> This patch fixes a long standing bug where aligned_operand ignores
> alignment of memory operand less than 32 bits. It drops address
> decomposition and returns false if alignment of memory operand less
> is than 32 bits. Tested on Linux/x86-64.
While trying to reduce the PR64835 case for ARM and x86, I noticed that
the alignment flags are cleared for x86 when attribute optimized is used.
With the attached testcases, the visible effects are twofold :
1) Functions compiled in with attribute optimize (-O2) are not aligned
as if they wer
On Wed, Feb 4, 2015 at 10:36 AM, Matthew Wahab wrote:
> Hello,
>
> The Cortex-A72 is an ARMv8 core with the same architectural features as the
> Cortex-A57. This patch adds support for the command line option
> -mcpu=cortex-a72 with the same effect as the -mcpu=cortex-a57 option, with
> only the n
On Wed, Feb 04, 2015 at 01:23:06PM +, Ramana Radhakrishnan wrote:
> On Wed, Feb 4, 2015 at 10:36 AM, Matthew Wahab wrote:
> > Hello,
> >
> > The Cortex-A72 is an ARMv8 core with the same architectural features as the
> > Cortex-A57. This patch adds support for the command line option
> > -mcpu
On Wed, Feb 04, 2015 at 12:57:11PM +, Marcus Shawcroft wrote:
> On 4 February 2015 at 10:35, Matthew Wahab wrote:
> > Hello,
> >
> > The Cortex-A72 is an ARMv8 core with the same architectural features as the
> > Cortex-A57. This patch adds support for the command line option
> > -mcpu=cortex-
Hi Guys,
I am checking in the patch below to add SUBREG to the list of rtx
codes accepted by the di_operand and nonimmediate_di_operand
predicates in the FR30 backend. This should resolve PR 64408.
Cheers
Nick
gcc/ChangeLog
2015-02-04 Nick Clifton
PR target/64408
* c
On 04/02/15 13:37, James Greenhalgh wrote:
On Wed, Feb 04, 2015 at 01:23:06PM +, Ramana Radhakrishnan wrote:
On Wed, Feb 4, 2015 at 10:36 AM, Matthew Wahab wrote:
Hello,
The Cortex-A72 is an ARMv8 core with the same architectural features as the
Cortex-A57. This patch adds support for th
On Wed, Feb 4, 2015 at 2:21 PM, Uros Bizjak wrote:
> On Mon, Feb 2, 2015 at 10:39 PM, H.J. Lu wrote:
>> This patch fixes a long standing bug where aligned_operand ignores
>> alignment of memory operand less than 32 bits. It drops address
>> decomposition and returns false if alignment of memory
On Wed, Feb 04, 2015 at 12:55:55PM +0100, Jakub Jelinek wrote:
> On Wed, Feb 04, 2015 at 03:48:38AM -0800, Segher Boessenkool wrote:
> > These testcases currently XPASS on most targets and configs, so let's
> > reduce the noise. Okay for mainline?
>
> Doesn't look like that is the case. obj69 is
Dear All,
Please find attached a reworked version of the patch for this PR. I
have no idea at all, why the original version worked for array
components on my laptop. In this version, the treatment of scalar and
array components is cleanly separated.
Bootstrapped and regtested on FC21/x86_64. OK f
Fix for a trivial but confusing typo in the jit docs.
Committed to trunk as r220408.
gcc/jit/ChangeLog:
* docs/topics/contexts.rst (gcc_jit_context_acquire): Fix
typo.
* docs/_build/texinfo/libgccjit.texi: Regenerate.
---
gcc/jit/docs/topics/contexts.rst | 2 +-
1 file c
On Tue, 3 Feb 2015 23:01:04 +0300
Ilya Verbin wrote:
> On 03 Feb 13:00, Julian Brown wrote:
> > On Tue, 3 Feb 2015 14:28:44 +0300
> > Ilya Verbin wrote:
> > > On 27 Jan 14:07, Julian Brown wrote:
> > > > On Mon, 26 Jan 2015 17:34:26 +0300
> > > > Ilya Verbin wrote:
> > > > > Here is my current
Ok.
>>If you're going to insist on calling the release_input_file API from
>>the claim_file handler, I'm going to have to fix gold to ignore the
>>call to avoid a premature unlock of the object file.
>
> What's the proper solution for not leaking those filedescriptors?
There was a bug in gold where it
On Wed, Feb 4, 2015 at 7:35 AM, Cary Coutant wrote:
>>>If you're going to insist on calling the release_input_file API from
>>>the claim_file handler, I'm going to have to fix gold to ignore the
>>>call to avoid a premature unlock of the object file.
>>
>> What's the proper solution for not leakin
When hard frame pointer isn't needed, the register for hard frame pointer
may be reused. This patch clears alignment on hard frame pointer if hard
frame pointer isn't needed. OK for trunk after bootstrap and test on
Linux/x86-64?
Thanks.
H.J.
--
gcc/
PR rtl-optimization/64905
On Wed, Feb 04, 2015 at 08:10:35AM -0600, Segher Boessenkool wrote:
> On a native i686 there are only four fails (the one with linker plugin works).
Yeah, I wrap linker because it is 64-bit and thus doesn't support 32-bit
plugins.
> I can xfail 41447 for ia32 if you want? The change for 41616 is
Hello,
This patch documents in gcc-5/changes.html the addition of support for
the Cortex-A72 to the ARM and the AArch64 backends.
Tested by checking the updated webpage in firefox.
Matthew
Index: htdocs/gcc-5/changes.html
===
RCS
Hi Catherine,
I've made a first pass at writing up the MIPS changes for GCC 5.0.
Could you take a read and see what needs some more work?
Thanks,
Matthew
Index: htdocs/gcc-5/changes.html
===
On Wed, Feb 4, 2015 at 8:46 AM, Matthew Fortune
wrote:
> Hi Catherine,
>
> I've made a first pass at writing up the MIPS changes for GCC 5.0.
> Could you take a read and see what needs some more work?
One comment below.
>
> Thanks,
> Matthew
>
> Index: htdocs/gcc-5/changes.html
> ==
Andrew Pinski writes:
> On Wed, Feb 4, 2015 at 8:46 AM, Matthew Fortune
> wrote:
> > Hi Catherine,
> >
> > I've made a first pass at writing up the MIPS changes for GCC 5.0.
> > Could you take a read and see what needs some more work?
>
> One comment below.
>
> >> Support for the Cavium Net
On Feb 4, 2015, at 2:28 AM, Rainer Orth wrote:
> Rainer Orth writes:
>>> On Jan 28, 2015, Mike Stump wrote:
On Jan 28, 2015, at 2:27 AM, Rainer Orth
wrote:
>
> * Remove the definition of _XOPEN_SOURCE completely.
I think I prefer this one…
and there is no hint wh
On Wednesday 2015-02-04 16:19, Matthew Wahab wrote:
This patch documents in gcc-5/changes.html the addition of
support for the Cortex-A72 to the ARM and the AArch64 backends.
Looks good to me, but you may want to wait a bit for ARMers to
chime in. Or go ahead and thing can always be tweaked l
On Wed, Feb 4, 2015 at 9:07 AM, Mike Stump wrote:
> On Feb 4, 2015, at 2:28 AM, Rainer Orth wrote:
>> Rainer Orth writes:
On Jan 28, 2015, Mike Stump wrote:
> On Jan 28, 2015, at 2:27 AM, Rainer Orth
> wrote:
>>
>> * Remove the definition of _XOPEN_SOURCE completely.
>
>>
Hi,
On 12 Dec 11:46, Thomas Schwinge wrote:
> On Tue, 21 Oct 2014 21:20:34 +0400, Ilya Verbin wrote:
> > This patch contains liboffloadmic library.
>
> > liboffloadmic/
> > Initial commit. Imported from upstream:
> > https://www.openmprtl.org/sites/default/files/liboffload_oss.tgz
> >
On Wed, Feb 04, 2015 at 08:44:42PM +0300, Ilya Verbin wrote:
> contrib/
> * gcc_update (files_and_dependencies): Add rules for liboffloadmic and
> liboffloadmic/plugin.
Ok, thanks.
Jakub
On Tue, Feb 3, 2015 at 11:10 AM, Mark Wielaard wrote:
> On Tue, 2015-02-03 at 19:59 +0100, Jan Kratochvil wrote:
>> On Tue, 03 Feb 2015 19:50:40 +0100, Doug Evans wrote:
>> > On Fri, Jan 16, 2015 at 2:42 PM, Jan Kratochvil
>> > wrote:
>> > > [...]
>> > > It is wrong that gcc puts -fpreprocessed i
To build the jit docs, we need to use sphinx 1.0 or later; the
0.6.6 in EPEL 6 doesn't support all the directives we need.
The alternate python-sphinx10 in EPEL 6 has 1.0.8:
python-sphinx10-1.0.8-1.el6.noarch
which is able to build the jit docs, apart from not having the
"pyramid" theme (this th
On Tue, Feb 3, 2015 at 5:16 PM, H.J. Lu wrote:
> On Tue, Feb 3, 2015 at 2:19 PM, Jakub Jelinek wrote:
>> On Tue, Feb 03, 2015 at 02:03:14PM -0800, H.J. Lu wrote:
>>> So we aren't SYMBOL_REF_EXTERNAL_P nor
>>> SYMBOL_REF_LOCAL_P. What do we reference?
>>
>> That is reasonable. There is no guaran
On Wed, Feb 04, 2015 at 10:27:34AM -0800, Sriraman Tallam wrote:
> On Tue, Feb 3, 2015 at 5:16 PM, H.J. Lu wrote:
> > On Tue, Feb 3, 2015 at 2:19 PM, Jakub Jelinek wrote:
> >> On Tue, Feb 03, 2015 at 02:03:14PM -0800, H.J. Lu wrote:
> >>> So we aren't SYMBOL_REF_EXTERNAL_P nor
> >>> SYMBOL_REF_LO
On Wed, Feb 4, 2015 at 10:31 AM, Jakub Jelinek wrote:
> On Wed, Feb 04, 2015 at 10:27:34AM -0800, Sriraman Tallam wrote:
>> On Tue, Feb 3, 2015 at 5:16 PM, H.J. Lu wrote:
>> > On Tue, Feb 3, 2015 at 2:19 PM, Jakub Jelinek wrote:
>> >> On Tue, Feb 03, 2015 at 02:03:14PM -0800, H.J. Lu wrote:
>> >
On Wed, Feb 04, 2015 at 10:38:48AM -0800, H.J. Lu wrote:
> Common symbol should be resolved locally for PIE.
binds_local_p yes, binds_to_current_def_p no.
Jakub
On Wed, Feb 4, 2015 at 10:42 AM, Jakub Jelinek wrote:
> On Wed, Feb 04, 2015 at 10:38:48AM -0800, H.J. Lu wrote:
>> Common symbol should be resolved locally for PIE.
>
> binds_local_p yes, binds_to_current_def_p no.
>
Is SYMBOL_REF_LOCAL_P set to binds_local_p or
binds_to_current_def_p?
--
H.J
Apologies for the slow response.
On Mon, 26 Jan 2015, Kai-Uwe Eckhardt wrote:
according to gcc/MAINTAINERS Jason and Krister are NetBSD
maintainers for GCC and can approve patches like yours, so
let me copy them.
(Should this be applied now, at least the copyright years
need to be adjusted to
On Wednesday 2015-02-04 13:32, David Malcolm wrote:
> OK for trunk?
>
> gcc/jit/ChangeLog:
> PR jit/64257
> * docs/conf.py (html_theme): Change from 'pyramid'
> to 'sphinxdoc'.
>
> maintainer-scripts/ChangeLog:
> PR jit/64257
> * update_web_docs_svn: Update build of
On Wed, Feb 4, 2015 at 10:45 AM, H.J. Lu wrote:
> On Wed, Feb 4, 2015 at 10:42 AM, Jakub Jelinek wrote:
>> On Wed, Feb 04, 2015 at 10:38:48AM -0800, H.J. Lu wrote:
>>> Common symbol should be resolved locally for PIE.
>>
>> binds_local_p yes, binds_to_current_def_p no.
>>
>
> Is SYMBOL_REF_LOCAL_
On Wed, Feb 4, 2015 at 10:51 AM, Sriraman Tallam wrote:
> On Wed, Feb 4, 2015 at 10:45 AM, H.J. Lu wrote:
>> On Wed, Feb 4, 2015 at 10:42 AM, Jakub Jelinek wrote:
>>> On Wed, Feb 04, 2015 at 10:38:48AM -0800, H.J. Lu wrote:
Common symbol should be resolved locally for PIE.
>>>
>>> binds_loc
On Wed, 2015-02-04 at 19:47 +0100, Gerald Pfeifer wrote:
> On Wednesday 2015-02-04 13:32, David Malcolm wrote:
> > OK for trunk?
> >
> > gcc/jit/ChangeLog:
> > PR jit/64257
> > * docs/conf.py (html_theme): Change from 'pyramid'
> > to 'sphinxdoc'.
> >
> > maintainer-scripts/ChangeLog:
On 2015-02-04 11:16 AM, H.J. Lu wrote:
When hard frame pointer isn't needed, the register for hard frame pointer
may be reused. This patch clears alignment on hard frame pointer if hard
frame pointer isn't needed. OK for trunk after bootstrap and test on
Linux/x86-64?
LRA can set up frame_poin
Hi!
I'd like to ping 2 patches:
http://gcc.gnu.org/ml/gcc-patches/2015-01/msg02530.html
- P2 - PR61925 - fix x86 #pragma GCC target handling
http://gcc.gnu.org/ml/gcc-patches/2015-01/msg02432.html
- emit DW_LANG_Fortran{03,08} for -gdwarf-5
Jakub
On Wed, Feb 4, 2015 at 11:20 AM, Vladimir Makarov wrote:
>
> On 2015-02-04 11:16 AM, H.J. Lu wrote:
>>
>> When hard frame pointer isn't needed, the register for hard frame pointer
>> may be reused. This patch clears alignment on hard frame pointer if hard
>> frame pointer isn't needed. OK for tr
Hi,
this is second attempt to fix the issue with arguments being passed
to builtlin_unreachable after
https://gcc.gnu.org/ml/gcc-patches/2014-12/msg01025.html
As suggested, I fixup the IL right after redirection instead waiting for
tree-ssa-dce.
Bootstrapped/regtested x86_64-linux, OK?
On Wed, Feb 04, 2015 at 08:47:20PM +0100, Jan Hubicka wrote:
> Bootstrapped/regtested x86_64-linux, OK?
> PR middle-end/64922
> * gimple.c: Include gimple-ssa.h
Missing dot at the end of line.
> (maybe_remove_unused_call_args): New function.
> * gimple.h (maybe_remove_unus
Dear Paul, dear all,
Paul Richard Thomas wrote:
Please find attached a reworked version of the patch for this PR. [...]
In this version, the treatment of scalar and array components is cleanly
separated.
Bootstrapped and regtested on FC21/x86_64. OK for trunk?
Looks good to me. Thanks for the
Hi,
The attached patch stops the recursion in the detection of FSM jump-threads at
loop phi nodes after having visited a loop phi node. This avoids jump-threading
two iterations forward that were possible due to a flip-flop operation that
exchange the value of the switch control variable as illus
On Wednesday 2015-02-04 14:10, David Malcolm wrote:
> Gerald: Please can you do the "svn up" on the relevant machine again,
> so that it gets the updated "update_web_docs_svn"?
That was my plan, yes. :-) I just did that and manually ran
the script, and it seems to work.
Still, do you think you
Hi Matthew,
I made a few edits. I removed the markup in the process, so that will need to
be added back.
See the text at the end.
Thanks,
Catherine
> -Original Message-
> From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> Sent: Wednesday, February 04, 2015 11:46 AM
> To: Moore
On Wed, Feb 4, 2015 at 10:57 AM, H.J. Lu wrote:
> On Wed, Feb 4, 2015 at 10:51 AM, Sriraman Tallam wrote:
>> On Wed, Feb 4, 2015 at 10:45 AM, H.J. Lu wrote:
>>> On Wed, Feb 4, 2015 at 10:42 AM, Jakub Jelinek wrote:
On Wed, Feb 04, 2015 at 10:38:48AM -0800, H.J. Lu wrote:
> Common symbo
> DW_LANG_Fortran03 and DW_LANG_Fortran08 DW_AT_language values were recently
> accepted into DWARF5. This patch changes GCC to handle those similarly to
> how e.g. the -std=c++11, -std=c++14 or -std=c11 are handled.
>
> As it will take some time for consumers to catch up, I'm enabling that
> only
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