New German PO file for 'gcc' (version 4.6.0)

Hello, gentle maintainer. This is a message from the Translation Project robot. A revised PO file for textual domain 'gcc' has been submitted by the German team of translators. The file is available at: http://translationproject.org/latest/gcc/de.po (This file, 'gcc-4.6.0.de.po', has just

Re: [pph] Moved token cache streaming to in/out respectively (issue4635073)

On Mon, Jun 27, 2011 at 15:32, wrote: > On 2011/06/27 18:51:22, Gabriel Charette wrote: > >> 2011-06-27  Gabriel Charette   > >>        * pph-streamer-in.c (pth_get_type_from_index): Moved from pph.c. >>        (pth_load_number): Moved from pph.c. >>        (pth_load_tok

[pph] Rename token cache and identifiers streaming functions to reflect pph naming scheme (issue4636065)

Renamed all functions to reflect pph naming schemes (pph_in/out_*). Also reordered parameters so that the first parameter is always pph_stream* Tested with bootstrap and pph regression testing. 2011-06-27 Gabriel Charette * pph-streamer-in.c (pph_get_type_from_index): Rename

Re: [pph] Rename token cache and identifiers streaming functions to reflect pph naming scheme (issue4636065)

On 2011/06/27 20:33:26, Gabriel Charette wrote: 2011-06-27 Gabriel Charette Remove the 'mailto:' prefix. * pph-streamer-in.c (pph_get_type_from_index): Rename from pth_get_type_from_index. Update all users. (pph_in_number): Rename from pth

Re: PATCH [10/n]: Prepare x32: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const

On Mon, Jun 27, 2011 at 11:59 AM, Ulrich Weigand wrote: > H.J. Lu wrote: > >> Reloads for insn # 588 >> Reload 0: reload_in (DI) =3D (reg/v/f:DI 182 [ b ]) >>         GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D 0) >>         reload_in_reg: (reg/v/f:DI 182 [ b ]) >>         reload_reg_rtx:

Re: [PATCH 0/4] Docs: extend.texi

On Thu, Apr 28, 2011 at 01:20, Michael Witten wrote: > See the following emails for a few inlined patches > to /trunk/gcc/doc/extend.texi (revision 172911): > > [1] Docs: extend.texi: Add missing semicolon for consistency > [2] Docs: extend.texi: Remove trailing blanks from lines > [3] Docs: e

Re: [RFA:] Removing target-libiberty on branches

> Date: Fri, 24 Jun 2011 10:14:13 +0200 > From: Richard Guenther > On Thu, Jun 23, 2011 at 8:23 PM, Hans-Peter Nilsson > wrote: > > Here's the patch I tested for 4.6, native > > x86_64-unknown-linux-gnu, cross to cris-axis-elf, both with old > > and new ("breaking") newlib. > > > > Ok for 4.6 an

Re: [PATCH][RFC][2/2] Bitfield lowering

On Mon, 27 Jun 2011, Richard Henderson wrote: > On 06/23/2011 02:49 AM, Richard Guenther wrote: > > So, do you know of a target that can do insv with a memory > > target? I would expect extv on memory to be easily doable. > > Depends on what you mean by that. INSV is the traditional > md patter

Re: Fix cgraph_address_taken_from_non_vtable_p

On Mon, 27 Jun 2011, Jan Hubicka wrote: > Hi, > this patch fixes thinko in cgraph_address_taken_from_non_vtable_p that valks > references in NODE instead of references of NODE. > It fixes the testcase in http://sourceware.org/bugzilla/show_bug.cgi?id=12942 > in non-plugin LTO and Gold, but not wit

Re: PATCH [10/n]: Prepare x32: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const

On Mon, Jun 27, 2011 at 1:42 PM, H.J. Lu wrote: > On Mon, Jun 27, 2011 at 11:59 AM, Ulrich Weigand wrote: >> H.J. Lu wrote: >> >>> Reloads for insn # 588 >>> Reload 0: reload_in (DI) =3D (reg/v/f:DI 182 [ b ]) >>>         GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum =3D 0) >>>         reload_i

Add Gabriel Charette to Write After Approval list (issue4626079)

Added myself to write after approval maintainers list. 2011-06-27 Gabriel Charette * MAINTAINERS (Write After Approval): Add myself. diff --git a/MAINTAINERS b/MAINTAINERS index 9dead4f..f6a768e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -324,6 +324,7 @@ Christian Bruel

Re: PATCH [10/n]: Prepare x32: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const

H.J. Lu wrote: > reload generates: > > (insn 914 912 0 (set (reg:SI 0 ax) > (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) > (const_int 8 [0x8]))) 248 {*lea_1_x32} > (nil)) > > from > > insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in)); Interesting.

[patch, fortran] Fix PR 49479, reshape with optional arg

Hello world, the attached patch fixes PR 49479, a regression for 4.7 and 4.6. Test case was supplied by Joost, the approach to the patch was suggested by Tobias in comment#4 of the PR. The patch certainly looks safe enough. Regression-tested. OK for trunk and, after a couple of days, for 4.6?

Re: PATCH [10/n]: Prepare x32: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const

On Mon, Jun 27, 2011 at 3:08 PM, Ulrich Weigand wrote: > H.J. Lu wrote: > >> reload generates: >> >> (insn 914 912 0 (set (reg:SI 0 ax) >>         (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) >>             (const_int 8 [0x8]))) 248 {*lea_1_x32} >>      (nil)) >> >> from >> >> insn = emit_insn_if

Re: PATCH [10/n]: Prepare x32: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const

On Mon, Jun 27, 2011 at 3:19 PM, H.J. Lu wrote: > On Mon, Jun 27, 2011 at 3:08 PM, Ulrich Weigand wrote: >> H.J. Lu wrote: >> >>> reload generates: >>> >>> (insn 914 912 0 (set (reg:SI 0 ax) >>>         (plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) >>>             (const_int 8 [0x8]))) 248 {*lea_

Re: [pph] Rename token cache and identifiers streaming functions to reflect pph naming scheme (issue4636065)

On Mon, Jun 27, 2011 at 1:40 PM, wrote: > > On 2011/06/27 20:33:26, Gabriel Charette wrote: >> >> 2011-06-27  Gabriel Charette   > > Remove the 'mailto:' prefix. Weird, that's not in the actual patch, probably gmail putting it in... Commited as rev r175568. Gab > > >

RE: Backport AVX256 load/store split patches to gcc 4.6 for performance boost on latest AMD/Intel hardware.

Hi, Attached are the patches we propose to backport to gcc 4.6 branch which are related to avx256 unaligned load/store splitting. As we mentioned before, The combined effect of these patches are positive on both AMD and Intel CPUs on cpu2006 and polyhedron 2005. 0001-Split-32-byte-AVX-unaligne

RE: [PATCH, i386] Enable -mprefer-avx128 by default for Bulldozer

Is this patch OK to commit to trunk? Also I would like to backport this patch to gcc 4.6 branch. Do I have to send a separate request or use this one? Thanks, Changpeng From: Fang, Changpeng Sent: Friday, June 24, 2011 7:12 PM To: Jan Hubicka Cc: Ur

Re: PATCH [10/n]: Prepare x32: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const

On Mon, Jun 27, 2011 at 3:25 PM, H.J. Lu wrote: > On Mon, Jun 27, 2011 at 3:19 PM, H.J. Lu wrote: >> On Mon, Jun 27, 2011 at 3:08 PM, Ulrich Weigand wrote: >>> H.J. Lu wrote: >>> reload generates: (insn 914 912 0 (set (reg:SI 0 ax)         (plus:SI (subreg:SI (reg/v/f:DI 182

Re: [RFC] Fix full memory barrier on SPARC-V8

From: Eric Botcazou Date: Mon, 27 Jun 2011 18:11:10 +0200 > * config/sparc/sync.md (*stbar): Delete. > (*membar_v8): New insn to implement UNSPEC_MEMBAR in SPARC-V8. Code which cares about memory ordering etc. really has to know the kind of cpu it is running on. This is why atomic a

[google] Enable both ld and gold in gcc (issue4664051)

This patch enables both ld and gold in gcc using the -fuse-ld switch. The original patch use written by Nick Clifton and was subsequently updated by Matthias Klose. The patch currently does not work with LTO but that is okay for now and it is no worse than its counterpart in an older gcc version.

Re: [google] Enable both ld and gold in gcc (issue4664051)

On Mon, Jun 27, 2011 at 4:09 PM, Doug Kwan wrote: > This patch enables both ld and gold in gcc using the -fuse-ld switch.  The > original patch use written by Nick Clifton and was subsequently updated by > Matthias Klose.  The patch currently does not work with LTO but that is > okay for now and i

Re: [RFC] Fix full memory barrier on SPARC-V8

On Jun 27, 2011, at 19:00, David Miller wrote: > V8 can only reorder stores, that's why it only has a 'stbar' > instruction. I'm not so sure I agree with trying to paper over the > fact that someone has compiled code for v8 that's going to run on a v9 > cpu. That's not the issue. While it is t

Re: [RFC] Fix full memory barrier on SPARC-V8

From: Geert Bosch Date: Mon, 27 Jun 2011 19:36:06 -0400 > On Jun 27, 2011, at 19:00, David Miller wrote: > >> V8 can only reorder stores, that's why it only has a 'stbar' >> instruction. I'm not so sure I agree with trying to paper over the >> fact that someone has compiled code for v8 that's

Re: [testsuite] ARM: don't specify unneeded -march

On Jun 21, 2011, at 2:48 PM, Janis Johnson wrote: > I modified these tests last week to check for thumb support and to > ignore messages about conflicting options, but -march isn't needed > and so there shouldn't be any conflicting options. > > OK? Ok.

Split insn-attr.h

opts.c includes insn-attr.h to get the definitions of INSN_SCHEDULING and DELAY_SLOTS, used to determine whether to enable certain options by default at certain -O levels. insn-attr.h in turn requires rtl.h to have been included first (and rtl.h requires tm.h, although there are other tm.h depende

[pph] Fix var order when streaming in. (issue4635074)

The names and namespaces chains are built by adding each new element to the front of the list. When streaming it in we traverse the list of names and re-add them to the current chains; thus reversing the order in which they were defined in the header file. Since this is a singly linked-list we

Re: Split insn-attr.h

On 06/28/11 02:24, Joseph S. Myers wrote: > > * genattr-common.c: New. Based on genattr.c. > * Makefile.in (INSN_ATTR_H): Include insn-attr-common.h. > (MOSTLYCLEANFILES): Add insn-attr-common.h. > (opts.o): Update dependencies. > (.PRECIOUS): Add insn-attr-common.h.

[pph] Update Tests (issue4636066)

Add missing mappings in pph.map. These new mappings result in changes to assembly difference expectations. Remove namespace issues from x1template test. Copy that test to a new test x1namespace. Add a new test x1dynarray, which is executable, when existing failures get fixed. Index: gcc/tests

Re: [patch, fortran] Fix PR 49479, reshape with optional arg

On 06/27/2011 03:18 PM, Thomas Koenig wrote: Hello world, the attached patch fixes PR 49479, a regression for 4.7 and 4.6. Test case was supplied by Joost, the approach to the patch was suggested by Tobias in comment#4 of the PR. The patch certainly looks safe enough. Regression-tested. OK for

Re: [RFC] Fix full memory barrier on SPARC-V8

On Jun 27, 2011, at 19:53, David Miller wrote: > I'm trying to find the part of the v8 manual that says there is > a situation where we should use "stbar" and a "ldstub" to implement > proper memory barriers. In particular I'm looking in Appendix J, > "Programming with the memory models." Where

Re: [RFC] Fix full memory barrier on SPARC-V8

From: Geert Bosch Date: Mon, 27 Jun 2011 22:21:47 -0400 > On Jun 27, 2011, at 19:53, David Miller wrote: > >> Adding a ldstub here is going to be really expensive, on UltraSparc >> that can be 36+ cycles even on a cache hit. > > Yes, synchronization in multi-CPU systems is expensive. > If it's

Re: [RFC] Fix full memory barrier on SPARC-V8

From: David Miller Date: Mon, 27 Jun 2011 19:45:33 -0700 (PDT) > You then go on to speak about LEON, does LEON implement PSO? BTW, even if it does, I would be encouraging the person who submits LEON kernel patches to not run the chip in this mode. We don't even use PSO for v9 chips, it's just n

Re: [RFC] Fix full memory barrier on SPARC-V8

On Jun 27, 2011, at 22:45, David Miller wrote: > From: Geert Bosch > Date: Mon, 27 Jun 2011 22:21:47 -0400 > >> On Jun 27, 2011, at 19:53, David Miller wrote: >> >>> Adding a ldstub here is going to be really expensive, on UltraSparc >>> that can be 36+ cycles even on a cache hit. >> >> Yes,

Re: [RFC] Fix full memory barrier on SPARC-V8

From: Geert Bosch Date: Mon, 27 Jun 2011 23:17:18 -0400 >> \You then go on to speak about LEON, does LEON implement PSO? > No, I'm not talking about PSO anywhere or SPARCv9 anywhere. > Just plain old SPARCv8, using the TSO model. This requires a > load-store instruction to guarantee a full memor

Re: [Patch, AVR]: AVR backend cleanup: use elfos.h

2011/6/27 Georg-Johann Lay : > or > > [ ] Remove the undefs so that we have .ident. >    There's nothing terrific about it, it just adds >    some text to .comment section.  I guess it's missing >    because noone ever added it. This one. Denis.

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