On 10/26/18, Uros Bizjak wrote:
> On Fri, Oct 26, 2018 at 9:37 AM Uros Bizjak wrote:
>>
>> On Fri, Oct 26, 2018 at 9:35 AM Uros Bizjak wrote:
>> >
>> > On Fri, Oct 26, 2018 at 9:19 AM H.J. Lu wrote:
>> > >
>> > > On 10/25/18, Uros Bizjak wrote:
>> > > > On Fri, Oct 26, 2018 at 8:07 AM H.J. Lu
On Fri, Oct 26, 2018 at 9:37 AM Uros Bizjak wrote:
>
> On Fri, Oct 26, 2018 at 9:35 AM Uros Bizjak wrote:
> >
> > On Fri, Oct 26, 2018 at 9:19 AM H.J. Lu wrote:
> > >
> > > On 10/25/18, Uros Bizjak wrote:
> > > > On Fri, Oct 26, 2018 at 8:07 AM H.J. Lu wrote:
> > > >>
> > > >> Many x86 pmovzx/
On Fri, Oct 26, 2018 at 9:35 AM Uros Bizjak wrote:
>
> On Fri, Oct 26, 2018 at 9:19 AM H.J. Lu wrote:
> >
> > On 10/25/18, Uros Bizjak wrote:
> > > On Fri, Oct 26, 2018 at 8:07 AM H.J. Lu wrote:
> > >>
> > >> Many x86 pmovzx/pmovsx instructions with memory operands are modeled in
> > >> a wrong
On Fri, Oct 26, 2018 at 9:19 AM H.J. Lu wrote:
>
> On 10/25/18, Uros Bizjak wrote:
> > On Fri, Oct 26, 2018 at 8:07 AM H.J. Lu wrote:
> >>
> >> Many x86 pmovzx/pmovsx instructions with memory operands are modeled in
> >> a wrong way. For example:
> >>
> >> (define_insn "sse4_1_v8qiv8hi2"
> >>
On 10/25/18, Uros Bizjak wrote:
> On Fri, Oct 26, 2018 at 8:07 AM H.J. Lu wrote:
>>
>> Many x86 pmovzx/pmovsx instructions with memory operands are modeled in
>> a wrong way. For example:
>>
>> (define_insn "sse4_1_v8qiv8hi2"
>> [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
>>