Is the patch with !TARGET_XTHEADVECTOR for sext/zext
patterns removed OK to commit?
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642657.html
--
发件人：juzhe.zh...@rivai.ai
发送时间：2024年1月11日(星期四) 18:56
收件人："cooper.joshua";
"g
pattern.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 20:31
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intri
it is 1.
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 20:18
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
No, we h
ode_for_pred_vf2 (, mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
}
[(set_attr "type" "vext")
(set_attr "mode" "")])
juzhe.zh...@rivai.ai
发件人： joshua
发送时间： 2024-01-11 20:05
收件人： juzhe.zh...@rivai.ai; gcc-patches
抄送： Ji
ches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
The sext/zext issue is not related to xtheadvector-special patterns.
I added !TARGET_XTHEADVECTOR to sext/zext patter
t; "")])
+
+(define_insn "@pred_indexed_store_width"
+ [(set (mem:BLK (scratch))
+ (unspec:BLK
+ [(unspec:
+ [(match_operand: 0 "vector_mask_operand" "vmWc1")
+ (match_operand 4 "vector_length_operand" " rK
ches
抄送： Jim Wilson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
Maybe the optimization cannot be done in simple cases. We run some complex cases
in O2 and dsicovered it.
---
[(unspec:
+ [(match_operand: 0 "vector_mask_operand" "vmWc1")
+ (match_operand 4 "vector_length_operand" " rK")
+ (match_operand 5 "const_int_operand" " i")
+ (reg:SI VL_REGNUM)
+
Maybe the optimization cannot be done in simple cases. We run some complex cases
in O2 and dsicovered it.
--
发件人：juzhe.zh...@rivai.ai
发送时间：2024年1月11日(星期四) 17:17
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew
"I didn't see theadvector-specific extension patterns. Could you show me?"
They are all in the file thead-vector.md.
For the sext/zext issue, perhaps I need some time to reproduce that
optimization,
but I can clearly remember it is related to vwmul.
-
lson; palmer; andrew; philipp.tomsich; jeffreyalaw;
christoph.muellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
The key difference between vlb/vlh/vlw is not output type too.
Their difference is the range of datatype, not one specific type.
We h
quot;
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu"
主 题：Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
The key difference between vlb/vlh/vlw is not output type too.
Their dif
uellner; jinma; cooper.qu
主题： Re：Re：[PATCH v5] RISC-V: Add support for xtheadvector-specific intrinsics.
Hi Juzhe,
Perhaps things are not as simple as imagined.
The differences between vlb/vlh/vlw is not the same
as vle8/vle16/vle32. "8", "16" or "32" in vle8
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