Re: web ICEs on subreg

2013-05-17 Thread Mike Stump
On May 16, 2013, at 5:26 PM, David Edelsohn wrote: > This patch is creating new segfaults for 32 bit POWER AIX. Thanks for the heads up. Fixed in r199030. 2013-05-17 Mike Stump PR rtl-optimization/57304 * web.c (union_match_dups): Ensure that DF_REF_LOC exists before

Re: web ICEs on subreg

2013-05-16 Thread Mike Stump
On May 16, 2013, at 5:26 PM, David Edelsohn wrote: > This patch is creating new segfaults for 32 bit POWER AIX. Was this > patch tested with PowerPC? No, x86_64. I've added a patch to http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57304 If you could let us know if that fixes the problem you've

Re: web ICEs on subreg

2013-05-16 Thread David Edelsohn
Mike, This patch is creating new segfaults for 32 bit POWER AIX. Was this patch tested with PowerPC? Program received signal SIGSEGV, Segmentation fault. 0x10a1db88 in _ZL8web_mainv () at /nasfarm/dje/src/src/gcc/web.c:138 138 if (DF_REF_REAL_LOC (*ref) == recog_data.operand_loc[op]

Re: web ICEs on subreg

2013-05-14 Thread Mike Stump
On May 10, 2013, at 5:27 PM, Kenneth Zadeck wrote: > Assuming the patch has been tested on a public port, it is ok for commit. Thanks. It turns out that my patch is necessary, but not sufficient, the code that exists must be left in place, as there are pre-existing test cases in the test suite

Re: web ICEs on subreg

2013-05-10 Thread Kenneth Zadeck
Assuming the patch has been tested on a public port, it is ok for commit. kenny On 05/10/2013 06:52 PM, Mike Stump wrote: On May 10, 2013, at 3:29 PM, Steven Bosscher wrote: Your web.c patch looks correct to me, but I can't approve it. Thanks. Now that you point out the DF accessor, it all m

Re: web ICEs on subreg

2013-05-10 Thread Mike Stump
On May 10, 2013, at 3:29 PM, Steven Bosscher wrote: > Your web.c patch looks correct to me, but I can't approve it. Thanks. Now that you point out the DF accessor, it all makes perfect sense. :-) I've fixed one other instance that has to be as wrong for all the same reasons. Though my port

Re: web ICEs on subreg

2013-05-10 Thread Steven Bosscher
On Fri, May 10, 2013 at 11:51 PM, Mike Stump wrote: > I have a instruction pattern for my port that reads in part: > > [(parallel [(set (subreg:DI (match_operand:TI 0 "register_operand" "=r") 0) >(mem:DI (plus:DI (match_operand:DI 1 "register_operand" > "r") >

Re: web ICEs on subreg

2013-05-10 Thread Steven Bosscher
On Fri, May 10, 2013 at 11:51 PM, Mike Stump wrote: > - if (DF_REF_LOC (*ref) == recog_data.operand_loc[op]) > - break; > + { > + if (DF_REF_LOC (*ref) == recog_data.operand_loc[op]) > + break; > + /* DF_REF_LOC can be (subreg:DI (reg:TI 5) 8) and > +