will have a try for this approach.
>
> Pan
>
> From: juzhe.zh...@rivai.ai
> Sent: Thursday, June 8, 2023 4:32 PM
> To: kito.cheng
> Cc: Li, Pan2 ; gcc-patches ;
> Robin Dapp ; jeffreyalaw ; Wang,
> Yanzhang
> Subject: Re: Re: [PATCH v8] RISC-V: Refactor requirement of
, Yanzhang
Subject: Re: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I have an idea base on what Kito said.
We enable vfadd FP16 for TARGET_ZVFH. But we don't need to add TARGET_VECTOR &&
for each instruction.
We can reference riscv.md:
(define_attr "ext_enabled
I have an idea base on what Kito said.
We enable vfadd FP16 for TARGET_ZVFH. But we don't need to add TARGET_VECTOR &&
for each instruction.
We can reference riscv.md:
(define_attr "ext_enabled" "no,yes"
(cond [(eq_attr "ext" "base")
(const_string "yes")
(and (eq_attr "ext" "f")
Oh. Good suggestion. It's much better than my solution I think.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-08 15:58
To: juzhe.zh...@rivai.ai
CC: pan2.li; gcc-patches; Robin Dapp; jeffreyalaw; yanzhang.wang
Subject: Re: [PATCH v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
I am
