Thank you for your reply. I am gonna try another to implement the fractional
vector spilling of RVV in RISC-V backend.
If this patch is really having a bad impact on other targets. I think this
patch may needs to be abandon.
juzhe.zh...@rivai.ai
From: Richard Sandiford
Date: 2022-07-27 20:
-V backend insert vsetvli after
RA (register allocation) so that it will not enlarge the spill size. Thank you
so much.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-07-27 20:56
To: juzhe.zh...@rivai.ai
CC: gcc-patches; vmakarov
Subject: Re: Re: [PATCH 1/1] Fix bit-position comparison
Biener
> Date: 2022-07-27 16:12
> To: juzhe.zh...@rivai.ai
> CC: gcc-patches
> Subject: Re: Re: [PATCH 1/1] Fix bit-position comparison
> On Wed, 27 Jul 2022, juzhe.zh...@rivai.ai wrote:
>
> > Let's take look at these 2 cases: https://godbolt.org/z/zP16frPnb. In
&
...@rivai.ai
CC: gcc-patches
Subject: Re: Re: [PATCH 1/1] Fix bit-position comparison
On Wed, 27 Jul 2022, juzhe.zh...@rivai.ai wrote:
> Let's take look at these 2 cases: https://godbolt.org/z/zP16frPnb. In
> RVV, we have vle8 and vsetvli to specify loading vint8mf2 (vsetvli a1,
>
zh...@rivai.ai
>
> From: Richard Biener
> Date: 2022-07-27 15:35
> To: juzhe.zh...@rivai.ai
> CC: gcc-patches
> Subject: Re: Re: [PATCH 1/1] Fix bit-position comparison
> On Wed, 27 Jul 2022, juzhe.zh...@rivai.ai wrote:
>
> > Thank you so much for the fast reply. Ok
I want to define
the machine_mode for `vint8mf2` with smaller element-size but same byte-size
from `vint8m1'.
Thank you for your reply.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2022-07-27 15:35
To: juzhe.zh...@rivai.ai
CC: gcc-patches
Subject: Re: Re: [PATCH 1/1] Fix bit-posi
On Wed, 27 Jul 2022, juzhe.zh...@rivai.ai wrote:
> Thank you so much for the fast reply. Ok, it is true that I didn't think
> about it carefully. Can you help me with the following the issue?
>
> For RVV (RISC-V 'V' Extension), we have full vector type 'vint8m1_t' (LMUL =
> 1) and fractional ve
Thank you so much for the fast reply. Ok, it is true that I didn't think about
it carefully. Can you help me with the following the issue?
For RVV (RISC-V 'V' Extension), we have full vector type 'vint8m1_t' (LMUL = 1)
and fractional vector type 'vint8mf2_t' (LMUL = 1/2).
Because in the ISA, we
