Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

2023-11-13 Thread 钟居哲
I just checked your test. I won't be brittle in the future. Since it should be 4 vsetvls with e16m1 for SLP AVL/VL toggling. And also it is no scheduling. The middle-end MIN_EXPR SLP always produce 4 AVL/VL toggling as long as we don't schedule the instructions. So it won't be problem. So, LGTM

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

2023-11-13 Thread juzhe.zh...@rivai.ai
--- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_zbb_run-2.c @@ -0,0 +1,19 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zbb --param riscv-autovec-preference=fixed-vlmax" } */ Could you add compile test (with asse

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

2023-11-13 Thread juzhe.zh...@rivai.ai
For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout the entire function, and could validly be replaced in all its occurrences by @var{op}. (``Validly'' here refers to the data flow of the program; simple replacement may make some insns invalid.) For example, when a constant is

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

2023-11-13 Thread juzhe.zh...@rivai.ai
I just checked definition of REG_EQUAL and REG_EQUIV. As you said, REG_EQUIV is more reasonable. Agree with use rtx_equal_p on REG_EQUIV and skip REG_EQUAL. Could you check whether it does fix your issues ? juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 17:25 To: juzhe.zh...@rivai.ai

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

2023-11-13 Thread juzhe.zh...@rivai.ai
Also, like kito previous remind me: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635326.html I think you should add a dedicated test which with specifying -march=rv64gcv_zbb, then scan-assembler-check the correct vsetvl. So that we can allow people like me be able to avoid regressio

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

2023-11-13 Thread juzhe.zh...@rivai.ai
Sorry. It should be return note1 && note2 && note1 == note2; juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:12 To: juzhe.zh...@rivai.ai; gcc-patches; palmer; kito.cheng; jeffreyalaw CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality. > Does this patch fixes

Re: Re: [PATCH] RISC-V: vsetvl: Refine REG_EQUAL equality.

2023-11-13 Thread juzhe.zh...@rivai.ai
I know the root cause is: (reg:DI 15 a5 [orig:175 _103 ] [175])(reg:DI 15 a5 [orig:174 _100 ] [174]) is considered as true on rtx_equal_p. I think return note1 == note2; will simplify your codes and fix this issue. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-13 16:12 To: juzhe.zh...