Re: Re: [PATCH] RISC-V: Support non-SLP unordered reduction

2023-07-17 Thread juzhe.zh...@rivai.ai
Address comment. V2 patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624638.html I added: +/* Change insn and Assert the change always happens. */ +static void +validate_change_or_fail (rtx object, rtx *loc, rtx new_rtx, bool in_group) +{ + bool change_p = validate_change (object, l

RE: Re: [PATCH] RISC-V: Support non-SLP unordered reduction

2023-07-15 Thread Li, Pan2 via Gcc-patches
: Friday, July 14, 2023 8:51 PM To: kito.cheng Cc: gcc-patches ; kito.cheng ; palmer ; rdapp.gcc ; Jeff Law Subject: Re: Re: [PATCH] RISC-V: Support non-SLP unordered reduction So to be safe, I think it should be backport to GCC 13 even though I didn't have a intrinsic testcase to reprodu

Re: Re: [PATCH] RISC-V: Support non-SLP unordered reduction

2023-07-14 Thread 钟居哲
So to be safe, I think it should be backport to GCC 13 even though I didn't have a intrinsic testcase to reproduce it. juzhe.zh...@rivai.ai From: Kito Cheng Date: 2023-07-14 20:38 To: 钟居哲 CC: GCC Patches; Kito Cheng; Palmer Dabbelt; Robin Dapp; Jeff Law Subject: Re: [PATCH] RISC-V: Support no

Re: Re: [PATCH] RISC-V: Support non-SLP unordered reduction

2023-07-14 Thread 钟居哲
>> It's performance bug or correctness bug? Does it's also appeared in gcc 13 >> if it's a correctness bug? It's correctness bug. The bug as below: vsetvli zero, 1, e16, m1, ta, ma > VSETVL pass detect it can be fused as "t1,zero,e16,m2,ta,ma" but failed in change_insn vmv.s.x v1,a5 ...