Re: Re: [PATCH] RISC-V: Support RVV VLA SLP auto-vectorization

Hi, Thanks kito.. I have added comments as you suggested. >> Do we have check builder.npatterns () must be power of 2 in somewhere? I also added: /* We don't enable SLP for non-power of 2 NPATTERNS. */ if (!pow2p_hwi (d->perm.encoding().npatterns ())) return false; too. To make sure we

Re: Re: [PATCH] RISC-V: Support RVV VLA SLP auto-vectorization

I compare the codegen with aarch64: https://godbolt.org/z/xTxPGcYMj asm of aarch64: f: add x5, x1, 7 mov x2, 0 cntbx4 ptrue p7.b, all adrpx3, .LC0 add x3, x3, :lo12:.LC0 index z30.b, #0, #8 ld1rd z29.d, p7/z