On Wed, 8 Nov 2023, Kito Cheng wrote:
> OK, then LGTM, thanks for the explanation :)
Please don't top-post on a GCC mailing list (and preferably in off-list
replies to such mailing list messages unless it's been agreed to somehow
with the participants), as it makes it difficult to make context
On Wed, Nov 8, 2023 at 2:37 PM juzhe.zh...@rivai.ai
wrote:
>
> Another question raise to me.
>
> Is it necessary we have such many variant of vsetvls?
>
> I am thinking about redesign:
>
> __riscv_vsetvl_e8mf8
> __riscv_vsetvl_e16mf4
> __riscv_vsetvl_e32mf2
> __riscv_vsetvl_e64m1
>
> They are quit
:
__riscv_vsetvl_ratio64
I am no proposing it since it has been used for a long time. Just raise my
concern.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-11-08 14:33
To: juzhe.zh...@rivai.ai
CC: gcc-patches; Kito.cheng; jeffreyalaw; Robin Dapp
Subject: Re: Re: [PATCH] RISC-V: Normalize user vsetvl
OK, then LGTM, thanks for the explanation :)
On Wed, Nov 8, 2023 at 2:33 PM juzhe.zh...@rivai.ai
wrote:
>
> More details:
>
> bb 1 bb 2
> \/
>bb 3
>
> VSETVL PASS can only do VSETVL demand fusion, fuse demand from bb 3 to bb 1,
> and fuse demand from bb 3 to bb2.
> We are not able to
More details:
bb 1 bb 2
\/
bb 3
VSETVL PASS can only do VSETVL demand fusion, fuse demand from bb 3 to bb 1,
and fuse demand from bb 3 to bb2.
We are not able to remove block bb 1 and bb 2 and create new bb 4 to hold the
vsetvl if bb 1 and bb 2 has the same vsetvl:
bb 4 (new block)
before VSETVL PASS. The code is as follows:
bb 1:
vsetvli e16mf2 -> set a6
bb 2:
vsetvli e32m1 -> set a6
bb 3:
...
vle (use a6) e32m1 TU
vle (use a6) e32m1 TU
vse (use a6) e32m1 TU
VSETVL PASS only do VSETVL information fusion, it doesn't do the CFG block
fusion.
VSETVL PASS succeed on followi
