Re: Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-16 Thread 钟居哲
>> Most likely than not you end up loading a larger quantity with the high >> bits zero'd. Interesting that we're using a packed model. I'd been >> told it was fairly expensive to implement in hardware relative to teh >> cost of implementing the sparse model. >> I'm a bit confused by this. GCC

Re: Re: [PATCH] RISC-V: Fix RVV mask mode size

2022-12-16 Thread 钟居哲
Yes, VNx4DF only has 4 bit in mask mode in case of load and store. For example vlm or vsm we will load store 8-bit ??? (I am not sure hardward can load store 4bit,but I am sure it definetly not load store the whole register size) So ideally it should be model more accurate. However, since GCC ass