Re: Re: [PATCH] RISC-V: Fix PR108279

2023-04-11 Thread juzhe.zhong
I don't want to seperate VSETVL PASS into 2 seperate PASS. I want make everything cleaner. Another example is VSETVL PASS can do the branch prediction: https://godbolt.org/z/K44r98E5v In function "f", you can see we put the hoist vsetvl from a more likely block (i !=cond) outside the loop, then

Re: Re: [PATCH] RISC-V: Fix PR108279

2023-04-11 Thread juzhe.zh...@rivai.ai
i From: Richard Biener Date: 2023-04-11 19:19 To: juzhe.zh...@rivai.ai CC: jeffreyalaw; gcc-patches; kito.cheng; palmer Subject: Re: Re: [PATCH] RISC-V: Fix PR108279 On Tue, Apr 11, 2023 at 11:19 AM juzhe.zh...@rivai.ai wrote: > > No, we can only pass "available" to LCM. > Passing

Re: Re: [PATCH] RISC-V: Fix PR108279

2023-04-11 Thread Richard Biener via Gcc-patches
ailable for both "vadd" and "vle32", > so LCM will hoist "vsetvl e8,mf8,TU" outside the LOOP > and remove all vsetvls inside the loop. > > > juzhe.zh...@rivai.ai > > > From: Richard Biener > Date: 2023-04-11 16:55 &

Re: Re: [PATCH] RISC-V: Fix PR108279

2023-04-11 Thread juzhe.zh...@rivai.ai
available for both "vadd" and "vle32", so LCM will hoist "vsetvl e8,mf8,TU" outside the LOOP and remove all vsetvls inside the loop. juzhe.zh...@rivai.ai From: Richard Biener Date: 2023-04-11 16:55 To: juzhe.zhong CC: Jeff Law; gcc-patches; kito.cheng; palmer Su

Re: Re: [PATCH] RISC-V: Fix PR108279

2023-04-11 Thread Richard Biener via Gcc-patches
On Wed, Apr 5, 2023 at 3:53 PM wrote: > > >> So fusion in this context is really about identifying cases where two > >> configuration settings are equivalent and you "fuse" them together. > >> Presumably this is only going to be possible when the vector insns are > >> just doing data movement rath

Re: Re: [PATCH] RISC-V: Fix PR108279

2023-04-05 Thread juzhe.zhong
>> So fusion in this context is really about identifying cases where two >> configuration settings are equivalent and you "fuse" them together. >> Presumably this is only going to be possible when the vector insns are >> just doing data movement rather than actual computations? >> If my understand

Re: Re: [PATCH] RISC-V: Fix PR108279

2023-04-02 Thread juzhe.zhong
This point is seletected not because LCM but by Phase 3 (VL/VTYPE demand info backward fusion and propogation) which is I introduced into VSETVL PASS to enhance LCM && improve vsetvl instruction performance. This patch is to supress the Phase 3 too aggressive backward fusion and propagation to