a corner case. But I don't think making GET_MODE_SIZE
bigger than the real size is conservatively correct.
Thanks,
Richard
>
>
> juzhe.zh...@rivai.ai
>
> From: Richard Biener
> Date: 2023-03-02 16:25
> To: juzhe.zhong
> CC: richard.sandiford; pan2.li; gcc-patches; Pan
can narrow down the
> > problem to.
> >
> >
> > 1. Defined the real size of both the precision and mode size to align
> > the riscv ISA.
> > 2. Besides, make the general mode_size = precision_size / 8 is able to
> > take care of both the exact_div and the
:
> > https://godbolt.org/z/P9e1adrd3
> > foo:# @foo
> > vsetvli a2, zero, e8, mf8, ta, ma
> > vsm.v v0, (a0)
> > vsetvli a2, zero, e8, mf4, ta, ma
> > vlm.v v8, (a0)
> > vsm.v v8, (a1
n and have a nice day!
>
> Pan
>
> From: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
> mailto:juzhe.zh...@rivai.ai>>
> Sent: Wednesday, March 1, 2023 10:19 PM
> To: rguenther mailto:rguent...@suse.de>>
> Cc: richard.sandiford
> mailto:richard.sand
ke care of both the exact_div and the dividend less than the divisor (like
> 1/8 or 2/8) cases.
>
> Could you please share your professional suggestions about this? Thank you
> all again and have a nice day!
>
> Pan
>
> From: juzhe.zh...@rivai.ai
> Sent: Wednesday, March
generate"
Pan
From: Li, Pan2
Sent: Wednesday, March 1, 2023 23:42
To: juzhe.zh...@rivai.ai ; rguenther
Cc: richard.sandiford ; gcc-patches
; Pan Li ; kito.cheng
Subject: RE: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks all for so much valuable a
Li, Pan2
; kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
>> So given the above I think that modeling the size as being the same
>> but with accurate precision would work. It's then only the size of the
>> padding in bytes we cannot represen
g precision even though
they have same bytesize.
First we emit vsetvl e8mf8 +vsm for VNx1BI
Then we emit vsetvl e8mf8 + vlm for VNx2BI
Thanks.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-03-01 22:03
To: juzhe.zhong
CC: richard.sandiford; gcc-patches; Pan Li; pan2.li; kito.cheng
Subject: R
On Wed, 1 Mar 2023, Richard Biener wrote:
> On Wed, 1 Mar 2023, juzhe.zh...@rivai.ai wrote:
>
> > Let's me first introduce RVV load/store basics and stack allocation.
> > For scalable vector memory allocation, we allocate memory according to
> > machine vector-length.
> > To get this CPU vector
On Wed, 1 Mar 2023, juzhe.zh...@rivai.ai wrote:
> Let's me first introduce RVV load/store basics and stack allocation.
> For scalable vector memory allocation, we allocate memory according to
> machine vector-length.
> To get this CPU vector-length value (runtime invariant but compile time
> un
e aware of this . Thanks.
juzhe.zh...@rivai.ai
From: juzhe.zh...@rivai.ai
Date: 2023-03-01 21:50
To: richard.sandiford; gcc-patches
CC: rguenther; Pan Li; pan2.li; kito.cheng
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Let's me first introduce RVV load/store basi
Let's me first introduce RVV load/store basics and stack allocation.
For scalable vector memory allocation, we allocate memory according to machine
vector-length.
To get this CPU vector-length value (runtime invariant but compile time
unknown), we have an instruction call csrr vlenb.
For example
tches
Cc: incarnation.p.lee ; pan2.li
; Kito.cheng ; rguenther
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Actually, we just want to differentiate VNx1BI VNx2BI VNx4BI VNx8BI, and they
are considered the same in GCC which produce BUG in RVV currently.
This patch is j
will be hitten.
>>
>> if (!can_div_away_from_zero_p (mode_precision[E_%smode], BITS_PER_UNIT,
>> &mode_size[E_%smode]))
>> gcc_unreachable (); // Hit on [4, 4] of the self-test.
>>
>> Pan
>> ____
>> From: juzhe.zh
ford ; pan2.li
Cc: incarnation.p.lee ; gcc-patches
; Kito.cheng ; rguenther
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
>> Is it right that, for RVV, a load or store of [4,4] will access [8,8]
>>bits, even when that means accessing fully-unused b
>> Is it right that, for RVV, a load or store of [4,4] will access [8,8]
>>bits, even when that means accessing fully-unused bytes? E.g. 4+4X
>>when X=3 would be 16 bits/2 bytes of useful data, but a bitsize of
>>8+8X would be 32 bits/4 bytes. So a store of [8,8] for a precision
>>of [4,4] would
; jeffreyalaw
Subject: RE: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Hi Richard Sandiford,
Looks like you are busy and stuck in some important work right now, could you
please help to share something like ETA if possible? Then we may have a better
plan for the RVV intrinsic support
.
Pan
From: juzhe.zh...@rivai.ai
Sent: Friday, February 24, 2023 1:08 PM
To: kito.cheng ; Li, Pan2
Cc: richard.sandiford ; incarnation.p.lee
; gcc-patches ;
Kito.cheng ; rguenther ; jeffreyalaw
Subject: Re: Re: [PATCH] RISC-V: Bugfix for rvv bool mode precision adjustment
Hi,
It's b
Hi,
It's been a while since this patch is sent.
This patch is very important for us since we are going to release RVV intrinsic
support in GCC 13.
And this is the patch to fix bug:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108654
Can any one verifies this patch for us?
Thanks.
juzhe.zh...
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