Re: Re: [PATCH] RISC-V: Add conditional unary neg/abs/not autovec patterns

2023-08-22 Thread 钟居哲
>> It's certainly got the potential to get out of hand. And it's not just >> the vectorizer operations. I know of an architecture that can execute >> most of its ALU and loads/stores conditionally (not predication, but >> actual conditional ops) like target = (x COND Y) ? a << b ; a) Do you mea

Re: Re: [PATCH] RISC-V: Add conditional unary neg/abs/not autovec patterns

2023-08-22 Thread juzhe.zh...@rivai.ai
Yes, I agree long-term we want every-thing be optimized as early as possible. However, IMHO, it's impossible we can support every conditional patterns in the middle-end (match.pd). It's a really big number. For example, for sign_extend conversion, we have vsext.vf2 (vector SI -> vector DI),...