> Thanks!
You're welcome. I have also installed the attached patch which makes minor
tweaks and fixes various issues in comments which have bugged me for years,
the most glaring one being:
Similar issue for (SUBREG:M1 (REG:M2 ...) ...) for a hard register R where
either M1 is not val
From: Eric Botcazou
Date: Wed, 26 Oct 2011 00:22:26 +0200
>> Eric, could you please take a look again at your reload bug fix
>> first posted at:
>>
>> http://gcc.gnu.org/ml/gcc-patches/2009-11/msg01671.html
>>
>> It looks correct to me, and I can reproduce it with the VIS3 fp moves
>> enable
> Eric, could you please take a look again at your reload bug fix
> first posted at:
>
> http://gcc.gnu.org/ml/gcc-patches/2009-11/msg01671.html
>
> It looks correct to me, and I can reproduce it with the VIS3 fp moves
> enabled by simply adjusting the costs and register class preferences
> s
