> On Oct 1, 2020, at 11:20 AM, Richard Sandiford
> wrote:
>
> Qing Zhao writes:
>> Hi, Richard,
>>
>> To answer the question, which registers should be included in “ALL”.
>> I studied X86 hard register set in more details. And also consulted with
>> H.J.Lu, And found:
>>
>> In the curren
> On Oct 2, 2020, at 10:15 AM, Richard Sandiford
> wrote:
>
> Qing Zhao writes:
>>>
>>> Going back to the default hook, I guess one option is:
>>>
>>> rtx zero = CONST0_RTX (reg_raw_mode[regno]);
>>> rtx_insn *insn = emit_insn (gen_rtx_SET (regno_reg_rtx[regno], zero));
>>> if (!valid_i
Qing Zhao writes:
>>
>> Going back to the default hook, I guess one option is:
>>
>> rtx zero = CONST0_RTX (reg_raw_mode[regno]);
>> rtx_insn *insn = emit_insn (gen_rtx_SET (regno_reg_rtx[regno], zero));
>> if (!valid_insn_p (insn))
>> sorry (…);
>
> “Sorry” here will tell the user tha
>
> Going back to the default hook, I guess one option is:
>
> rtx zero = CONST0_RTX (reg_raw_mode[regno]);
> rtx_insn *insn = emit_insn (gen_rtx_SET (regno_reg_rtx[regno], zero));
> if (!valid_insn_p (insn))
> sorry (…);
“Sorry” here will tell the user that the implementation on th
> On Oct 1, 2020, at 11:20 AM, Richard Sandiford
> wrote:
>
> Qing Zhao writes:
>> Hi, Richard,
>>
>> To answer the question, which registers should be included in “ALL”.
>> I studied X86 hard register set in more details. And also consulted with
>> H.J.Lu, And found:
>>
>> In the curren
Qing Zhao writes:
> Hi, Richard,
>
> To answer the question, which registers should be included in “ALL”.
> I studied X86 hard register set in more details. And also consulted with
> H.J.Lu, And found:
>
> In the current x86 implementation, mask registers, MM0-MM7 registers, and
> ST0-ST7 regis
Hi, Richard,
To answer the question, which registers should be included in “ALL”.
I studied X86 hard register set in more details. And also consulted with
H.J.Lu, And found:
In the current x86 implementation, mask registers, MM0-MM7 registers, and
ST0-ST7 registers are not zeroed.
The reasons
> On Sep 30, 2020, at 11:25 AM, Richard Sandiford
> wrote:
>
> Qing Zhao writes:
As I checked, when the FP registers are zeroed, the above failure happened.
I suspect that the issue still relate to the following statement:
machine_mode mode = reg_raw_mode[reg
Qing Zhao writes:
>>> + }
>>> + return need_zeroed_hardregs;
>>> +}
>>> +
>>>
>>> With the small testing case:
>>> int
>>> test ()
>>> {
>>> return 1;
>>> }
>>>
>>> If I compiled it with
>>>
>>> /home/qinzhao/Install/latest/bin/gcc -O2 -fzero-call-used-regs=all-arg t.c
>>>
>>> It will
> On Sep 30, 2020, at 4:21 AM, Richard Sandiford
> wrote:
>
> Qing Zhao mailto:qing.z...@oracle.com>> writes:
>> Hi, Richard,
>>
>> At the same time testing aarch64, I also tested the default implementation
>> on rs6000 target.
>>
>> The default implementation now is:
>>
>> +/* The defau
Qing Zhao writes:
> Hi, Richard,
>
> At the same time testing aarch64, I also tested the default implementation on
> rs6000 target.
>
> The default implementation now is:
>
> +/* The default hook for TARGET_ZERO_CALL_USED_REGS. */
> +
> +HARD_REG_SET
> +default_zero_call_used_regs (HARD_REG_SET
Hi, Richard,
At the same time testing aarch64, I also tested the default implementation on
rs6000 target.
The default implementation now is:
+/* The default hook for TARGET_ZERO_CALL_USED_REGS. */
+
+HARD_REG_SET
+default_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)
+{
+ gcc_asser
> On Sep 25, 2020, at 12:31 PM, Richard Sandiford
> wrote:
>
> Qing Zhao writes:
>> Last question, in the following code portion:
>>
>> /* Now we get a hard register set that need to be zeroed, pass it to
>> target to generate zeroing sequence. */
>> HARD_REG_SET zeroed_hardregs;
>>
Qing Zhao writes:
> Last question, in the following code portion:
>
> /* Now we get a hard register set that need to be zeroed, pass it to
> target to generate zeroing sequence. */
> HARD_REG_SET zeroed_hardregs;
> start_sequence ();
> zeroed_hardregs = targetm.calls.zero_call_used_r
> On Sep 25, 2020, at 11:58 AM, Richard Sandiford
> wrote:
>
> Qing Zhao writes:
Which data structure in GCC should be used here to hold this returned
value as Set of RTX ?
>>>
>>> A HARD_REG_SET is enough. All the caller needs to know is: which registers
>>> were cl
Qing Zhao writes:
>> On Sep 25, 2020, at 10:28 AM, Richard Sandiford
>> wrote:
>>
>> Qing Zhao mailto:qing.z...@oracle.com>> writes:
On Sep 25, 2020, at 7:53 AM, Richard Sandiford
wrote:
Qing Zhao writes:
> Hi, Richard,
>
> As you suggested, I added a defaul
> On Sep 25, 2020, at 10:28 AM, Richard Sandiford
> wrote:
>
> Qing Zhao mailto:qing.z...@oracle.com>> writes:
>>> On Sep 25, 2020, at 7:53 AM, Richard Sandiford
>>> wrote:
>>>
>>> Qing Zhao writes:
Hi, Richard,
As you suggested, I added a default implementation of the tar
Qing Zhao writes:
>> On Sep 25, 2020, at 7:53 AM, Richard Sandiford
>> wrote:
>>
>> Qing Zhao writes:
>>> Hi, Richard,
>>>
>>> As you suggested, I added a default implementation of the target hook
>>> “zero_cal_used_regs (HARD_REG_SET)” as following in my latest patch
>>>
>>>
>>> /* The de
> On Sep 25, 2020, at 7:53 AM, Richard Sandiford
> wrote:
>
> Qing Zhao writes:
>> Hi, Richard,
>>
>> As you suggested, I added a default implementation of the target hook
>> “zero_cal_used_regs (HARD_REG_SET)” as following in my latest patch
>>
>>
>> /* The default hook for TARGET_ZERO_
Qing Zhao writes:
> Hi, Richard,
>
> As you suggested, I added a default implementation of the target hook
> “zero_cal_used_regs (HARD_REG_SET)” as following in my latest patch
>
>
> /* The default hook for TARGET_ZERO_CALL_USED_REGS. */
>
> void
> default_zero_call_used_regs (HARD_REG_SET need_
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