On Tue, May 8, 2018 at 5:56 PM, Richard Sandiford
wrote:
> Richard Biener writes:
>> On Tue, May 8, 2018 at 3:25 PM, Richard Sandiford
>> wrote:
>>> We build up the input to IFN_STORE_LANES one vector at a time.
>>> In RTL, each of these vector assignments becomes a write to
>>> subregs of the f
Richard Biener writes:
> On Tue, May 8, 2018 at 3:25 PM, Richard Sandiford
> wrote:
>> We build up the input to IFN_STORE_LANES one vector at a time.
>> In RTL, each of these vector assignments becomes a write to
>> subregs of the form (subreg:VEC (reg:AGGR R)), where R is the
>> eventual input t
On Tue, May 8, 2018 at 3:25 PM, Richard Sandiford
wrote:
> We build up the input to IFN_STORE_LANES one vector at a time.
> In RTL, each of these vector assignments becomes a write to
> subregs of the form (subreg:VEC (reg:AGGR R)), where R is the
> eventual input to the store lanes instruction.
