Re: [patch, mips] Size optimization for MIPS

2013-07-11 Thread Richard Sandiford
Steve Ellcey writes: > On Tue, 2013-07-09 at 18:25 +0100, Richard Sandiford wrote: >> That was always the case though. These registers weren't enabled because >> you can do operations on them. They were enabled because they should make >> ideal spill space. Moves to and from these registers alw

Re: [patch, mips] Size optimization for MIPS

2013-07-09 Thread Steve Ellcey
On Tue, 2013-07-09 at 18:25 +0100, Richard Sandiford wrote: > > That was always the case though. These registers weren't enabled because > you can do operations on them. They were enabled because they should make > ideal spill space. Moves to and from these registers always take 2 bytes, > whe

Re: [patch, mips] Size optimization for MIPS

2013-07-09 Thread Richard Sandiford
"Steve Ellcey " writes: > While doing some size measurements and optimization I found that using the > t0 through t7 registers on MIPS in MIPS16 mode resulted in larger code. This > is because you cannot actually do any operations on these registers in MIPS16 > mode but can only move data to or

Re: [patch, mips] Size optimization for MIPS

2013-07-09 Thread Richard Henderson
On 07/09/2013 09:29 AM, Steve Ellcey wrote: > + /* In MIPS16 mode using the $t registers for reload results in code > + that is larger (and slightly faster) then if we do not use them so > + if optimizing for size, do not use them. */ > + if (optimize_size) > + { > +