Re: [SPARC] Tidy up Condition Code support and more

2016-10-12 Thread Jose E. Marchesi
> Note that the ADDXC, ADDXCCC, SUBXC and SUBXCCC instructions do not > support immediate operands. Hence the patch breaks vis3-enabling arches > and niagara-7. Egad. I totally overlooked this (yet the -mcpu=niagara7 -m64 testsuite is rather explicit) and this is a bit

Re: [SPARC] Tidy up Condition Code support and more

2016-10-11 Thread Eric Botcazou
> Note that the ADDXC, ADDXCCC, SUBXC and SUBXCCC instructions do not > support immediate operands. Hence the patch breaks vis3-enabling arches > and niagara-7. Egad. I totally overlooked this (yet the -mcpu=niagara7 -m64 testsuite is rather explicit) and this is a bit of a shame, especially fo

Re: [SPARC] Tidy up Condition Code support and more

2016-10-11 Thread Jose E. Marchesi
Hi Eric. +(define_insn "*plus_sltu_vis3" + [(set (match_operand:W 0 "register_operand" "=r") + (plus:W (ltu:W (match_operand 2 "icc_register_operand" "X") + (const_int 0)) + (match_operand:W 1 "arith_operand" "rI")))] + "TARGET_ARCH64 && TARG