On 22/03/2020 18:15, Jérémy Lefaure wrote:
> Hi Wilco,
>
> On Mon, Mar 09, 2020 at 05:53:41PM +, Wilco Dijkstra wrote:
>> Hi,
>>
>> There is no single PC offset that is correct given CPUs may use different
>> offsets.
>
> Isn't it always an offset of 8 in ARM mode and 4 bytes in Thumb mode ?
Hi Wilco,
On Mon, Mar 09, 2020 at 05:53:41PM +, Wilco Dijkstra wrote:
> Hi,
>
> There is no single PC offset that is correct given CPUs may use different
> offsets.
Isn't it always an offset of 8 in ARM mode and 4 bytes in Thumb mode ?
At least in ARMv7 and in AArch32 state in ARMv8 ?
> G
Hi,
There is no single PC offset that is correct given CPUs may use different
offsets.
GCC may also schedule the instruction that stores the PC. This feature used to
work on early Arms but is no longer functional or useful today, so the best way
forward is to remove it altogether. There are many
Hi Sandra,
On Mon, Feb 24, 2020 at 02:19:21PM -0700, Sandra Loosemore wrote:
> On 2/20/20 3:08 PM, Jérémy Lefaure wrote:
> > Hello,
> >
> > Ping for https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01081.html.
> >
> > Thank you,
> > Jérémy
> >
> > On Sun, Dec 15, 2019 at 07:20:26PM +0100, Jérémy L
On 2/20/20 3:08 PM, Jérémy Lefaure wrote:
Hello,
Ping for https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01081.html.
Thank you,
Jérémy
On Sun, Dec 15, 2019 at 07:20:26PM +0100, Jérémy Lefaure wrote:
Hi!
Since in ARM state the value of PC is the address of the current
instruction plus 8 bytes,
