FYI:
This PR described the syntax of fli instruction, which is implemented
in LLVM, and the latest binutils patch (IIRC :P):
https://github.com/riscv-non-isa/riscv-asm-manual/pull/85
On 3/10/23 05:40, Jin Ma via Gcc-patches wrote:
This patch adds the 'Zfa' extension for riscv, which is based on:
https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
of this writing.
Thank you very much for your comments. Since a long time has passed and this is
an initial version, I will update this patch.
--
From:Christoph Müllner
Sent At:2023 Apr. 13 (Thu.) 17:22
To:Jin Ma
Cc:gcc-patches ; kito.cheng ;
kito.
On Fri, Mar 10, 2023 at 1:41 PM Jin Ma via Gcc-patches
wrote:
>
> This patch adds the 'Zfa' extension for riscv, which is based on:
>
> https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
> latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
On 3/10/23 05:40, Jin Ma via Gcc-patches wrote:
This patch adds the 'Zfa' extension for riscv, which is based on:
https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
of this writing.
