Re: [PATCH v5 2/3] RISC-V: Add crypto machine descriptions

2023-12-21 Thread Jeff Law
On 12/20/23 20:50, juzhe.zh...@rivai.ai wrote: + (and:VI + (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") + (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr"))) This order should be swapped like ARM SVE: (define_expand "@cond_bic"   [(se

Re: [PATCH v5 2/3] RISC-V: Add crypto machine descriptions

2023-12-20 Thread juzhe.zh...@rivai.ai
+ (and:VI + (match_operand:VI 3 "register_operand" "vr, vr, vr, vr") + (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr"))) This order should be swapped like ARM SVE: (define_expand "@cond_bic" [(set (match_operand:SVE_FULL_I 0 "register_operand") (u