Re: [PATCH v3] RISC-V: Implement TLS Descriptors.

> On Nov 21, 2023, at 15:59, Fangrui Song wrote: > > On Mon, Nov 20, 2023 at 6:20 AM Tatsuyuki Ishi > wrote: >> >> This implements TLS Descriptors (TLSDESC) as specified in [1]. >> >> The 4-instruction sequence is implemented as a single RTX insn for >> simplici

Re: [PATCH v3] RISC-V: Implement TLS Descriptors.

* Tatsuyuki Ishi: > There is, please see [1]. The vector register file handling is missing right > now as I’m not sure if we have agreed upon a calling convention for RVV. > [1]: > https://inbox.sourceware.org/libc-alpha/20230914084033.222120-1-ishitatsuy...@gmail.com/ Thank you, I have raised

Re: [PATCH v3] RISC-V: Implement TLS Descriptors.

> On Nov 23, 2023, at 19:57, Florian Weimer wrote: > > * Tatsuyuki Ishi: > >> I've considered gating this behind a GAS feature test, but it seems >> nontrivial especially for restricting the variants available at runtime. >> Since TLS descriptors is not selected by default, I've decided to leave

Re: [PATCH v3] RISC-V: Implement TLS Descriptors.

* Tatsuyuki Ishi: > I've considered gating this behind a GAS feature test, but it seems > nontrivial especially for restricting the variants available at runtime. > Since TLS descriptors is not selected by default, I've decided to leave it > ungated. > > In other news, I have made some progress on

Re: [PATCH v3] RISC-V: Implement TLS Descriptors.

> On Nov 21, 2023, at 15:59, Fangrui Song wrote: > > On Mon, Nov 20, 2023 at 6:20 AM Tatsuyuki Ishi > wrote: >> >> This implements TLS Descriptors (TLSDESC) as specified in [1]. >> >> The 4-instruction sequence is implemented as a single RTX insn for >> simplici

Re: [PATCH v3] RISC-V: Implement TLS Descriptors.

On Mon, Nov 20, 2023 at 6:20 AM Tatsuyuki Ishi wrote: > > This implements TLS Descriptors (TLSDESC) as specified in [1]. > > The 4-instruction sequence is implemented as a single RTX insn for > simplicity, but this can be revisited later if instruction scheduling or > more flexible RA is desired.