> >
> >> (insn 20 19 23 2 (set (reg/v:DI 200 [ val+-4 ])
> >> (sign_extend:DI (subreg:SI (reg/v:DI 200 [ val+-4 ]) 4)))
> >> "/app/example.cpp":7:29 -1
> >> (nil))
>
> Haven't had chance to compile and look at it properly, but this subreg
> seems suspicious for MIPS, given the definit
>
> Note I think Andrews comment#7 in the PR is spot-on then, the issue
> isn't the bitfield inserts but the compare where combine elides
> the sign_extend in favor of a subreg. That's likely some wrongdoing
> in simplify-rtx in the context of WORD_REGISTER_OPERATIONS.
>
Yes. There are 2 problems
Richard Biener writes:
#> On Thu, 20 Jul 2023, Richard Sandiford wrote:
>
>> Jeff Law via Gcc-patches writes:
>> > On 7/19/23 04:25, Richard Biener wrote:
>> >> On Wed, 19 Jul 2023, YunQiang Su wrote:
>> >>
>> >>> Eric Botcazou ?2023?7?19??? 17:45???
>>
>> > I don't see that. That's d
On Thu, 20 Jul 2023, Richard Sandiford wrote:
> Jeff Law via Gcc-patches writes:
> > On 7/19/23 04:25, Richard Biener wrote:
> >> On Wed, 19 Jul 2023, YunQiang Su wrote:
> >>
> >>> Eric Botcazou ?2023?7?19??? 17:45???
>
> > I don't see that. That's definitely not what GCC expects here
Jeff Law via Gcc-patches writes:
> On 7/19/23 04:25, Richard Biener wrote:
>> On Wed, 19 Jul 2023, YunQiang Su wrote:
>>
>>> Eric Botcazou ?2023?7?19??? 17:45???
> I don't see that. That's definitely not what GCC expects here,
> the left-most word of the doubleword should be unchan
On 7/19/23 04:25, Richard Biener wrote:
On Wed, 19 Jul 2023, YunQiang Su wrote:
Eric Botcazou ?2023?7?19??? 17:45???
I don't see that. That's definitely not what GCC expects here,
the left-most word of the doubleword should be unchanged.
Your testcase should be a dg-do-run and probably
On Wed, 19 Jul 2023, YunQiang Su wrote:
> Eric Botcazou ?2023?7?19??? 17:45???
> >
> > > I don't see that. That's definitely not what GCC expects here,
> > > the left-most word of the doubleword should be unchanged.
> > >
> > > Your testcase should be a dg-do-run and probably more like
> > >
> >
Eric Botcazou 于2023年7月19日周三 17:45写道：
>
> > I don't see that. That's definitely not what GCC expects here,
> > the left-most word of the doubleword should be unchanged.
> >
> > Your testcase should be a dg-do-run and probably more like
> >
> > NOMIPS16 int __attribute__((noipa)) test (const unsign
> I don't see that. That's definitely not what GCC expects here,
> the left-most word of the doubleword should be unchanged.
>
> Your testcase should be a dg-do-run and probably more like
>
> NOMIPS16 int __attribute__((noipa)) test (const unsigned char *buf)
> {
> int val;
> ((unsigned char
Richard Biener 于2023年7月19日周三 17:23写道：
>
> On Wed, 19 Jul 2023, YunQiang Su wrote:
>
> > Richard Biener ?2023?7?19??? 15:22???
> > >
> > > On Wed, 19 Jul 2023, YunQiang Su wrote:
> > >
> > > > Richard Biener via Gcc-patches ?2023?7?19???
> > > > 14:27???
> > > > >
> > > > > On Wed, 19 Jul 2023,
On Wed, 19 Jul 2023, Richard Biener wrote:
> On Wed, 19 Jul 2023, YunQiang Su wrote:
>
> > Richard Biener ?2023?7?19??? 15:22???
> > >
> > > On Wed, 19 Jul 2023, YunQiang Su wrote:
> > >
> > > > Richard Biener via Gcc-patches ?2023?7?19???
> > > > 14:27???
> > > > >
> > > > > On Wed, 19 Jul 20
On Wed, 19 Jul 2023, YunQiang Su wrote:
> Richard Biener ?2023?7?19??? 15:22???
> >
> > On Wed, 19 Jul 2023, YunQiang Su wrote:
> >
> > > Richard Biener via Gcc-patches ?2023?7?19???
> > > 14:27???
> > > >
> > > > On Wed, 19 Jul 2023, YunQiang Su wrote:
> > > >
> > > > > PR #104914
> > > > >
>
I am not sure this patch is best, while I think that I am sure the
initial RTL is not correct,
the initial RTL of ARM64 is like
(insn 8 7 9 2 (set (zero_extract:SI (reg/v:SI 98 [ val ])
^^
(const_int 8 [0x8])
(const_int 0 [0
YunQiang Su 于2023年7月19日周三 16:21写道：
>
> Richard Biener 于2023年7月19日周三 15:22写道：
> >
> > On Wed, 19 Jul 2023, YunQiang Su wrote:
> >
> > > Richard Biener via Gcc-patches ?2023?7?19???
> > > 14:27???
> > > >
> > > > On Wed, 19 Jul 2023, YunQiang Su wrote:
> > > >
> > > > > PR #104914
> > > > >
> > >
Richard Biener 于2023年7月19日周三 15:22写道：
>
> On Wed, 19 Jul 2023, YunQiang Su wrote:
>
> > Richard Biener via Gcc-patches ?2023?7?19???
> > 14:27???
> > >
> > > On Wed, 19 Jul 2023, YunQiang Su wrote:
> > >
> > > > PR #104914
> > > >
> > > > When work with
> > > > int val;
> > > > ((unsigned ch
On Wed, 19 Jul 2023, YunQiang Su wrote:
> Richard Biener via Gcc-patches ?2023?7?19???
> 14:27???
> >
> > On Wed, 19 Jul 2023, YunQiang Su wrote:
> >
> > > PR #104914
> > >
> > > When work with
> > > int val;
> > > ((unsigned char*)&val)[3] = *buf;
> > > if (val > 0) ...
> > > The RTX mode
Richard Biener via Gcc-patches 于2023年7月19日周三 14:27写道：
>
> On Wed, 19 Jul 2023, YunQiang Su wrote:
>
> > PR #104914
> >
> > When work with
> > int val;
> > ((unsigned char*)&val)[3] = *buf;
> > if (val > 0) ...
> > The RTX mode is obtained from REG instead of SUBREG, which make
> > D is used
On Wed, 19 Jul 2023, YunQiang Su wrote:
> PR #104914
>
> When work with
> int val;
> ((unsigned char*)&val)[3] = *buf;
> if (val > 0) ...
> The RTX mode is obtained from REG instead of SUBREG, which make
> D is used instead of . Thus something wrong happens
> on sign-extend default archite
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