Committed, thanks Jeff and Juzhe, sorry for misleading.
Pan
-Original Message-
From: Jeff Law
Sent: Thursday, June 15, 2023 2:51 AM
To: juzhe.zh...@rivai.ai; Li, Pan2 ; gcc-patches
Cc: Robin Dapp ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor
On 6/13/23 20:31, juzhe.zh...@rivai.ai wrote:
LGTM.
Similarly. If I've interpreted the thread correctly, there aren't any
issues created by this patch, though there are some existing issues that
need to be addressed independently. The patch itself is definitely the
right thing to be doing
om>;
jeffreyalaw<mailto:jeffreya...@gmail.com>;
yanzhang.wang<mailto:yanzhang.w...@intel.com>;
kito.cheng<mailto:kito.ch...@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for
define_insn_and_split
Yes, I agree with the general assessment (and didn't mean to i
> I am not sure. These testcases were added by kito long time ago.
> Frankly, I am not familiar with GCC test framework.
Ok, I'm going to have a look. Need to verify the zvfh things anyway.
Regards
Robin
cc; jeffreyalaw; yanzhang.wang; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for
define_insn_and_split
Yes, I agree with the general assessment (and didn't mean to insinuate
that the FAILs are compiler's or a fault of the patch.
> So these 2 failures in RV32 are not
Yes, I agree with the general assessment (and didn't mean to insinuate
that the FAILs are compiler's or a fault of the patch.
> So these 2 failures in RV32 are not the compile's bugs. I have seen:
> /* { dg-do run { target { { {riscv_vector} && {rv64} } } } } */ in
> these testcases which can not
gcc-patches
Cc: rdapp@gmail.com; jeffreyalaw ; Wang, Yanzhang
; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for
define_insn_and_split
> I don't have a proper sim environment setup yet. How long does the
> testsuite take
> with spike? Have you t
> I don't have a proper sim environment setup yet. How long does the
> testsuite take
> with spike? Have you tried qemu as well?
Any numbers on this Pan? How many cores do you use for running the testsuite?
Regards
Robin
Wang,
Yanzhang<mailto:yanzhang.w...@intel.com>;
kito.cheng<mailto:kito.ch...@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for
define_insn_and_split
Hi Pan,
these failures were present before the patch I suppose? They
don't look related. Is this what you mean
issues. So, we can go ahead.
Thanks.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-14 14:09
To: Li, Pan2; juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; jeffreyalaw; Wang, Yanzhang; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for
define_insn_and_split
H
Hi Pan,
these failures were present before the patch I suppose? They
don't look related. Is this what you meant by "the same as upstream"?
> FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c -std=c99 -O3
> -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for
> ex
e report -j $(nproc) RUNTESTFLAGS="rvv.exp"
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, June 14, 2023 10:31 AM
To: Li, Pan2 ; gcc-patches
Cc: Robin Dapp ; jeffreyalaw ; Li,
Pan2 ; Wang, Yanzhang ; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for
define_
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-14 10:15
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split
From: Pan Li
This patch is considered as the follow up
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