Re: [PATCH v1] RISC-V: Add testcases for vector unsigned SAT_SUB form 2

On 6/15/24 6:56 AM, pan2...@intel.com wrote: From: Pan Li The previous RISC-V backend .SAT_SUB enabling patch missed the form 2 testcases of vector modes. Aka: Form 2: #define DEF_VEC_SAT_U_SUB_FMT_2(T) \ void __attribute__((noinline))

Re: [PATCH v1] RISC-V: Add testcases for vector unsigned SAT_SUB form 2

lgtm --Reply to Message-- On Sat, Jun 15, 2024 20:56 PM Li, Pan2