Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

2022-11-18 Thread Philipp Tomsich
On Fri, 18 Nov 2022 at 15:34, Jeff Law wrote: > > > On 11/17/22 16:56, Palmer Dabbelt wrote: > > On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: > >> > >> On 11/12/22 14:29, Philipp Tomsich wrote: > >>> Users might use explicit arithmetic operations to create a mask and >

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

2022-11-18 Thread Jeff Law via Gcc-patches
On 11/17/22 16:56, Palmer Dabbelt wrote: On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: On 11/12/22 14:29, Philipp Tomsich wrote: Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1;    

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

2022-11-17 Thread Philipp Tomsich
On Fri, 18 Nov 2022 at 00:56, Palmer Dabbelt wrote: > > On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: > > > > On 11/12/22 14:29, Philipp Tomsich wrote: > >> Users might use explicit arithmetic operations to create a mask and > >> then and it, in a sequence like > >>

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

2022-11-17 Thread Philipp Tomsich
On Fri, 18 Nov 2022 at 00:41, Jeff Law wrote: > > > On 11/12/22 14:29, Philipp Tomsich wrote: > > Users might use explicit arithmetic operations to create a mask and > > then and it, in a sequence like > > cond = (bits >> SHIFT) & 1; > > mask = ~(cond - 1); > > val &= mask; > > whic

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

2022-11-17 Thread Palmer Dabbelt
On Thu, 17 Nov 2022 15:41:26 PST (-0800), gcc-patches@gcc.gnu.org wrote: On 11/12/22 14:29, Philipp Tomsich wrote: Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; whic

Re: [PATCH 4/7] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

2022-11-17 Thread Jeff Law via Gcc-patches
On 11/12/22 14:29, Philipp Tomsich wrote: Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; which will present as a single-bit sign-extract. Dependening on what combina