Re: Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

more reasonable. > > -- > juzhe.zh...@rivai.ai > > > *From:* Sergei Lewis > *Date:* 2023-12-11 22:58 > *To:* juzhe.zh...@rivai.ai > *CC:* gcc-patches ; Robin Dapp > ; Kito.cheng ; jeffreyalaw > > *Subject:* Re: [PATCH 2/3] RISC-V: setme

Re: Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

: Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension The thinking here is that using the largest possible LMUL when we know the operation will fit in fewer registers potentially leaves performance on the table - indirectly, due to the unnecessarily increased register pressure, and also

Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

The thinking here is that using the largest possible LMUL when we know the operation will fit in fewer registers potentially leaves performance on the table - indirectly, due to the unnecessarily increased register pressure, and also directly, depending on the implementation. On Mon, Dec 11, 2023

Re: [PATCH 2/3] RISC-V: setmem for RISCV with V extension

On Mon, Dec 11, 2023 at 5:48 PM Sergei Lewis wrote: > > gcc/ChangeLog > > * config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): New > function > declaration. > > * config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): New > function: this generates an inline v