Pushed. Thank you for your review,
Claudiu
On Tue, Jul 23, 2019 at 12:51 AM Jeff Law wrote:
>
> On 7/9/19 10:23 AM, claz...@gmail.com wrote:
> > Hi Jeff,
> >
> > Please find attached the updated patch.
> >
> > What is new:
> > - mailing list feedback is taken into account.
> > - some comments are
On 7/9/19 10:23 AM, claz...@gmail.com wrote:
> Hi Jeff,
>
> Please find attached the updated patch.
>
> What is new:
> - mailing list feedback is taken into account.
> - some comments are updated.
> - a new test is added.
> - the ARC AUX registers used by ZOL (hardware loop) and FPX (a custom
> f
Hi Jeff,
Please find attached the updated patch.
What is new:
- mailing list feedback is taken into account.
- some comments are updated.
- a new test is added.
- the ARC AUX registers used by ZOL (hardware loop) and FPX (a custom
floating point implementation) are saved before fp-register.
- the
On 7/8/19 2:35 AM, Claudiu Zissulescu wrote:
> Hi Jeff,
>
> Originally, I had the scheduler barrier as you suggested. However,
> there were some user cases when an ISR messed up with SP register
> leading to errors. As a solution was to add barriers on either part of
> frame operations. However, I
Hi Jeff,
Originally, I had the scheduler barrier as you suggested. However,
there were some user cases when an ISR messed up with SP register
leading to errors. As a solution was to add barriers on either part of
frame operations. However, I would need to recheck the original
rationale of that iss
On 6/28/19 7:39 AM, Claudiu Zissulescu wrote:
> When entering an interrupt, not only the call save registers needs to
> be place on stack but also the call clobbers one. More over, the
> ARC700 return from interrupt instruction needs to be rtie, the same
> like ARCv2 CPUs. While the ARC6xx family u
